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    Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
    1.
    发明授权
    Reliable BEOL integration process with direct CMP of porous SiCOH dielectric 有权
    可靠的BEOL集成工艺与多孔SiCOH电介质的直接CMP

    公开(公告)号：US07948083B2

    公开(公告)日：2011-05-24

    申请号：US11763135

    申请日：2007-06-14

    申请人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

    发明人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

    IPC分类号： H01L29/40

    CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

    摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法至少包括化学机械抛光和UV曝光或化学修复处理的步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

    Reliable BEOL integration process with direct CMP of porous SiCOH dielectric
    2.
    发明授权
    Reliable BEOL integration process with direct CMP of porous SiCOH dielectric 失效
    可靠的BEOL集成工艺与多孔SiCOH电介质的直接CMP

    公开(公告)号：US07253105B2

    公开(公告)日：2007-08-07

    申请号：US11063152

    申请日：2005-02-22

    申请人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

    发明人： Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Vincent J. McGahay ,  Sanjay C. Mehta

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

    摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

    Method to create region specific exposure in a layer
    6.
    发明授权
    Method to create region specific exposure in a layer 有权
    在图层中创建区域特定曝光的方法

    公开(公告)号：US07977032B2

    公开(公告)日：2011-07-12

    申请号：US10906268

    申请日：2005-02-11

    申请人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

    发明人： Christos D. Dimitrakopoulos ,  Daniel C. Edelstein ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Kevin S. Petrarca ,  Shom Ponoth ,  Shahab Siddiqui

    IPC分类号： G03F7/20

    CPC分类号： G03F7/2022

    摘要： A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

    摘要翻译： 提供了一种在邻接区域中对材料性质进行不同的改变的同时选择性地改变一个区域中的衬底的材料特性的方法。 该方法包括在第一曝光期间选择性地掩蔽衬底的第一部分，并且在第二次曝光期间选择性地掩蔽衬底的第二部分。 另外，可以形成具有多于一个厚度的掩模，其中每个厚度将选择性地减少来自衬底的覆盖曝光的能量的量，从而允许衬底在单次覆盖曝光中接收不同水平的能量。

    DEEP TRENCH CRACKSTOPS UNDER CONTACTS
    9.
    发明申请
    DEEP TRENCH CRACKSTOPS UNDER CONTACTS 失效
    DEEP TRENCH CRACKSTOPS UNDER联系人

    公开(公告)号：US20100200960A1

    公开(公告)日：2010-08-12

    申请号：US12689479

    申请日：2010-01-19

    申请人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

    发明人： Matthew S. Angyal ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Satyanarayana V. Nitta ,  Shaoning Yao

    IPC分类号： H01L23/544 ,  H01L21/302

    CPC分类号： H01L23/585 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

    摘要翻译： 形成在半导体衬底的接触电平下方的深沟槽作为裂纹，在晶片的管芯区域或划线区域中起作用，并且可以设置成距它们旨在保护的器件的距离增加的行，并且可以位于 在互连堆叠层中的格子工作裂纹结构下。 深沟槽可以保持未填充，或者可以用介电材料或导体填充。 深沟槽可以具有大约1微米至100微米的衬底的深度和约10nm至10微米的宽度。

    RUN-TIME DISPATCH SYSTEM FOR ENHANCED PRODUCT CHARACTERIZATION CAPABILITY
    10.
    发明申请
    RUN-TIME DISPATCH SYSTEM FOR ENHANCED PRODUCT CHARACTERIZATION CAPABILITY 失效
    运行时间分配系统，提高产品特性能力

    公开(公告)号：US20090149979A1

    公开(公告)日：2009-06-11

    申请号：US11951503

    申请日：2007-12-06

    申请人： Vincent J. McGahay

    发明人： Vincent J. McGahay

    IPC分类号： G06F19/00

    CPC分类号： G06Q10/06

    摘要： Disclosed herein are embodiments of an automated manufacturing system that is used to process multiple jobs in a product fabrication environment, where such processing comprises performing the same multiple consecutive process steps for each job and where each process step can be accomplished using one or more different available processing tools. The manufacturing system incorporates a unique run-time dispatch system. This dispatch system schedules the order in which jobs will be processed and further randomly assigns a particular combination of process steps and tools to each job in such a way that the processing tools are evenly distributed across the jobs. Ensuring even distribution of processing tools allows a statistical process control system to not only detect, for a given process step, product variability outside desired specifications, but also to efficiently de-convolve such product variability.

    摘要翻译： 这里公开的是用于在产品制造环境中处理多个作业的自动化制造系统的实施例，其中这样的处理包括为每个作业执行相同的多个连续的处理步骤，并且其中每个处理步骤可以使用一个或多个不同的可用 加工工具。 制造系统采用独特的运行时调度系统。 该调度系统调度处理作业的顺序，并进一步随机地将每个作业的特定组合处理步骤和工具分配给处理工具均匀地分布在作业中。 确保加工工具的均匀分配允许统计过程控制系统不仅针对给定的工艺步骤检测出期望规格之外的产品变异性，而且还有效地解除这种产品变异性。