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    Semiconductor memory devices for alternately selecting bit lines
    4.
    发明授权
    Semiconductor memory devices for alternately selecting bit lines 有权
    用于交替选择位线的半导体存储器件

    公开(公告)号：US09183910B2

    公开(公告)日：2015-11-10

    申请号：US13907223

    申请日：2013-05-31

    申请人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

    发明人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

    IPC分类号： G11C11/16 ,  G11C7/12

    CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

    摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

    摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）。

    Resistive memory devices and methods of controlling operations of the same
    6.
    发明授权
    Resistive memory devices and methods of controlling operations of the same 有权
    电阻式存储器件及其操作方法

    公开(公告)号：US08271856B2

    公开(公告)日：2012-09-18

    申请号：US12711416

    申请日：2010-02-24

    申请人： Sang-Beom Kang ,  Chul-Woo Park ,  Hyun-Ho Choi ,  Ho-Jung Kim

    发明人： Sang-Beom Kang ,  Chul-Woo Park ,  Hyun-Ho Choi ,  Ho-Jung Kim

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1048 ,  G11C13/0004 ,  G11C2029/0411

    摘要： To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.

    摘要翻译： 为了控制电阻性存储器件的操作，错误检查和校正（ECC）代码的输入输出操作与数据的输入输出操作分离。 确定ECC代码的输入输出操作的条件比数据的输入输出操作的条件更严格。 可以提高ECC代码的输入输出操作的可靠性，从而减少由于缺陷存储单元，噪声等导致的错误。

    Resistive Memory Devices and Methods of Controlling Operations of the Same
    8.
    发明申请
    Resistive Memory Devices and Methods of Controlling Operations of the Same 有权
    电阻式存储器件及其控制方法

    公开(公告)号：US20100218073A1

    公开(公告)日：2010-08-26

    申请号：US12711416

    申请日：2010-02-24

    申请人： Sang-Beom Kang ,  Chul-Woo Park ,  Hyun-Ho Choi ,  Ho-Jung Kim

    发明人： Sang-Beom Kang ,  Chul-Woo Park ,  Hyun-Ho Choi ,  Ho-Jung Kim

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G11C13/0004 ,  G11C2029/0411

    摘要： To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.

    摘要翻译： 为了控制电阻性存储器件的操作，错误检查和校正（ECC）代码的输入输出操作与数据的输入输出操作分离。 确定ECC代码的输入输出操作的条件比数据的输入输出操作的条件更严格。 可以提高ECC代码的输入输出操作的可靠性，从而减少由于缺陷存储单元，噪声等导致的错误。

    Resistive memory devices, memory systems and methods of controlling input and output operations of the same
    10.
    发明授权
    Resistive memory devices, memory systems and methods of controlling input and output operations of the same 有权
    电阻式存储器件，存储器系统和控制其输入和输出操作的方法

    公开(公告)号：US08223529B2

    公开(公告)日：2012-07-17

    申请号：US12703354

    申请日：2010-02-10

    申请人： Ho-Jung Kim ,  Yeong-Taek Lee ,  Chul-Woo Park ,  Sang-Beom Kang

    发明人： Ho-Jung Kim ,  Yeong-Taek Lee ,  Chul-Woo Park ,  Sang-Beom Kang

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C8/10 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/009

    摘要： A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage.

    摘要翻译： 电阻式存储器件包括电阻存储单元阵列，输出电路和输入电路。 电阻存储单元阵列包括耦合到位线的多个存储单元。 输出电路通过感测位线电压在写入操作期间产生感测输出信号，并通过感测位线电压在读取操作期间产生输出数据。 输入电路基于用于写入操作的输入数据来控制位线电压，并且在写入操作期间响应于感测输出信号来限制位线电压。 存储单元受到有效限制位线电压的保护。