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    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS
    6.
    发明申请
    GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS 有权
    GAP填充方法双重DAMASCENE过程

    公开(公告)号：US20120319278A1

    公开(公告)日：2012-12-20

    申请号：US13161701

    申请日：2011-06-16

    申请人： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    发明人： Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Syun-Ming Jang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/511 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

    摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括形成具有多个第一开口的图案化电介质层。 该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。 该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。 该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。 该方法包括去除沟槽掩模层。

    Differentially metal doped copper damascenes
    7.
    发明申请
    Differentially metal doped copper damascenes 审中-公开
    差异化金属掺杂铜大马士革

    公开(公告)号：US20060091551A1

    公开(公告)日：2006-05-04

    申请号：US10977596

    申请日：2004-10-29

    申请人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

    发明人： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  C25D3/58 ,  C25D5/022 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877

    摘要： A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

    摘要翻译： 一种形成具有改善的体积特性的铜填充半导体特征的方法，包括提供具有包括用于形成半导体特征的开口的工艺表面的半导体工艺晶片; 在所述开口上沉积至少一种含金属掺杂剂层以形成与随后沉积的铜层的热扩散关系; 沉积所述铜层以基本上填充所述开口; 以及对所述半导体工艺晶片进行热处理足以使所述金属掺杂剂的至少一部分分布在包含所述铜层晶界的一部分的所述铜层的周边的至少一部分的时间段内收集。

    Inflected magnetoresistive structures and memory cells having inflected magnetoresistive structures
    10.
    发明授权
    Inflected magnetoresistive structures and memory cells having inflected magnetoresistive structures 失效
    具有变形磁阻结构的变形磁阻结构和存储单元

    公开(公告)号：US07705340B2

    公开(公告)日：2010-04-27

    申请号：US11163118

    申请日：2005-10-05

    申请人： Chun-Chieh Lin

    发明人： Chun-Chieh Lin

    IPC分类号： H01L47/00

    CPC分类号： H01L27/228 ,  H01L43/08

    摘要： Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

    摘要翻译： 本文公开了具有非平面形式的磁阻结构。 本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。 这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。