公开(公告)号：US06645574B1

公开(公告)日：2003-11-11

申请号：US09719103

申请日：2000-12-06

申请人： Chun-Soo Lee ,  Won-Gu Kang ,  Kyu-Hong Lee ,  Kyoung-Soo Yi

发明人： Chun-Soo Lee ,  Won-Gu Kang ,  Kyu-Hong Lee ,  Kyoung-Soo Yi

IPC分类号： C23C1606

CPC分类号： C30B25/14 ,  C23C16/45529 ,  C23C16/4554 ,  C23C16/45561 ,  C23C16/515 ,  C23C16/56 ,  C30B25/105

摘要： A noble method of forming thin films for producing semiconductor or flat panel display devices is disclosed. The method is a way of effectively forming thin films on a substrate even if reactants do not react readily in a time-divisional process gas supply sequence in a reactor by supplying reactant gases and a purge gas cyclically and sequentially in order to prevent gas-phase reactions between the reactant gases and also by generating plasma directly on a substrate synchronously with the process gas supply cycle. The method has advantages of effective thin film formation even if the reactant gases do not react readily, minimization of the purge gas supply time for reduction in process time, reduction of particle contamination during film formation process, as well as thin film formation at low temperatures.

摘要翻译： 公开了一种形成用于制造半导体或平板显示装置的薄膜的高贵方法。 该方法是在基板上有效地形成薄膜的方法，即使反应物在反应器中的分时工艺气体供应顺序中不容易反应，通过循环和顺序地供应反应气体和吹扫气体来反应，以防止气相 反应气体之间的反应，也是通过与工艺气体供应循环同步在衬底上直接产生等离子体。 该方法具有有效的薄膜形成的优点，即使反应物气体不容易反应，减少吹扫气体供应时间以减少处理时间，减少成膜过程中的颗粒污染，以及在低温下形成薄膜 。

公开(公告)号：US06539891B1

公开(公告)日：2003-04-01

申请号：US09763238

申请日：2001-02-14

申请人： Chun-Soo Lee ,  Won-Gu Kang ,  Kyu-Hong Lee ,  Kyoung-Soo Yi

发明人： Chun-Soo Lee ,  Won-Gu Kang ,  Kyu-Hong Lee ,  Kyoung-Soo Yi

IPC分类号： C23C1600

CPC分类号： C23C16/515 ,  C23C16/4405 ,  C23C16/45536 ,  C23C16/45544 ,  C23C16/45561 ,  C23C16/45591 ,  C23C16/509

摘要： A chemical deposition reactor capable of switching rapidly from one process gas to another and method of forming a thin film using the same. The reactor of the present invention comprises: a reactor cover, having an inlet and an outlet, for keeping reactant gases from other part of the reactor where the pressure is lower than inside of the reactor; a gas flow control plate, fixed onto the reactor cover, for controlling the gas flow through inlet and outlet by the spacing between itself and the reactor cover; and a substrate supporting plate for confining a reaction cell with the reactor cover. The method of the present invention can be accomplished using the above reactor. In the method, process gases including a deposition gas, a reactant gas and a purge gas are sequentially and repeatedly supplied in the reactor to form a thin film on a substrate. A RF (Radio Frequency) plasma power is applied to a plasma electrode of the reactor synchronised with the supply of at least one among the process gases.

摘要翻译： 能够从一种工艺气体迅速地切换到另一种工艺气体的化学沉积反应器和使用其形成薄膜的方法。 本发明的反应器包括：具有入口和出口的反应器盖，用于保持来自反应器其他部分的反应气体，其中压力低于反应器内部; 固定在反应器盖上的气流控制板，用于通过入口和出口通过其本身与反应器盖之间的间隔来控制气流; 以及用于将反应池限制在反应器盖上的基板支撑板。 本发明的方法可以使用上述反应器来实现。 在该方法中，包括沉积气体，反应气体和吹扫气体的处理气体在反应器中顺序地和重复地供给，以在基板上形成薄膜。 将RF（射频）等离子体功率施加到反应器的等离子体电极，与处理气体中的至少一个的供给同步。

公开(公告)号：US5262670A

公开(公告)日：1993-11-16

申请号：US666248

申请日：1991-03-08

申请人： Jin-Hyo Lee ,  Kyu-Hong Lee ,  Dae-Yong Kim ,  Won-Gu Kang

发明人： Jin-Hyo Lee ,  Kyu-Hong Lee ,  Dae-Yong Kim ,  Won-Gu Kang

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L27/02

CPC分类号： H01L27/1023 ,  H01L21/8229 ,  Y10S257/906

摘要： A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

摘要翻译： 双极性DRAM包括开关晶体管，存储电容器和基板。 开关晶体管和存储电容器彼此垂直堆叠。 开关晶体管优选为NPN双极晶体管。 开关晶体管优选地包括P基极区域，衬底的N +发射极区域，N +集电极区域，在N +发射极区域和P基极区域之间具有下部外延层，以及在P基极区域之间的上部外延层 和N +集电极区域。 存储电容器包括形成在N +集电区域上的存储电极，电介质层和平板电极。 电介质层和平板电极在存储电极上垂直并顺序地堆叠。 在平板电极上形成位线，在P +基极区域的侧面上形成字线。

公开(公告)号：US5869881A

公开(公告)日：1999-02-09

申请号：US946009

申请日：1997-10-07

申请人： Kyu-Hong Lee ,  Jin-Hyo Lee

发明人： Kyu-Hong Lee ,  Jin-Hyo Lee

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  H01L29/732

摘要： The present invention relates to a pillar bipolar transistor and the fabricating method thereof, the active region on which the emitter region, the base region and the collector region are formed, is defined at the first pillar by the trench formed in the semiconductor substrate, a party of the base region and the polysilicon base electrode is electrically connected by the base connection, thereby decreasing the contact area and protecting to increase the extrinsic region of the base, and protecting to mask a juction of base to emitter at high concentration. Also, the polysilicon emitter electrode having the wide surface area is formed by self-aligned contact using the CMP method on the upper of the emitter region. Therefore, the active region of the transistor is defined in the first pillar, so that the parasitic capacitance between the emitter and the collector, and the base is decreased, and the contact area between the base region and the polysilicon base electrode is also decreased, thereby enhancing the operational characteristic of the transistor by protecting to increase the extrinsic region of the base, and the current gain similar to the forward operation of the transistor can be obtained in the backward operation of the transistor. Also, the emitter polysilicon electrode having the wide surface is self-arranged with the emitter region, thereby easily forming the contact opening to form the emitter electrode.

摘要翻译： 本发明涉及柱状双极晶体管及其制造方法，其中形成有发射极区域，基极区域和集电极区域的有源区域由形成在半导体衬底中的沟槽在第一支柱处限定， 基极区域和多晶硅基极电极通过基极连接电连接，从而减小接触面积并保护增加基极的外在区域，并且保护以高浓度掩蔽基极到发射极的切口。 此外，具有宽表面积的多晶硅发射极电极通过使用CMP方法的自对准接触形成在发射极区域的上部。 因此，晶体管的有源区域被限定在第一支柱中，使得发射极和集电极之间的寄生电容和基极减小，并且基极区域和多晶硅基极之间的接触面积也减小， 从而通过保护来提高晶体管的工作特性，以增加基极的非本征区域，并且可以在晶体管的反向工作中获得类似于晶体管正向工作的电流增益。 此外，具有宽表面的发射极多晶硅电极与发射极区域自配置，从而容易地形成接触开口以形成发射极电极。

公开(公告)号：US5747871A

公开(公告)日：1998-05-05

申请号：US696256

申请日：1996-08-13

申请人： Kyu-Hong Lee ,  Jin-Hyo Lee ,  Jong-Sun Lyu

发明人： Kyu-Hong Lee ,  Jin-Hyo Lee ,  Jong-Sun Lyu

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/70 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L31/11

CPC分类号： H01L29/66272 ,  H01L29/732

摘要： A bipolar transistor and a process for manufacturing thereof is disclosed. The bipolar transistor has a self-aligned base electrode in which first and second pillars are formed within first and second trenches which act as an activated region and a collector region, respectively; a conductive impurities layer of high density formed at a bottom side of the first and second trenches and at a lower portion of an isolation wall between the first and second trenches; and a sequentially formed base and emitter layer. After connection to the base layer, a base contact electrode is formed within the first trench, and a collector contact electrode is formed by implanting second conductive impurities in the second pillar.

摘要翻译： 公开了一种双极晶体管及其制造方法。 双极晶体管具有自对准基极，其中第一和第二柱分别形成在第一和第二沟槽内，其分别用作激活区域和集电极区域; 在第一和第二沟槽的底侧形成高密度的导电杂质层，以及在第一和第二沟槽之间的隔离壁的下部; 和顺序形成的基极和发射极层。 在连接到基底层之后，在第一沟槽内形成基极接触电极，通过在第二支柱中注入第二导电杂质形成集电极接触电极。

公开(公告)号：US5506157A

公开(公告)日：1996-04-09

申请号：US469677

申请日：1995-06-06

申请人： Kyu-Hong Lee ,  Jin-Hyo Lee

发明人： Kyu-Hong Lee ,  Jin-Hyo Lee

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  H01L29/732 ,  Y10S148/01 ,  Y10S148/011

摘要： Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed upward the first pillar to expose a surface of the first pillar; injecting an impurity in the first pillar to form a base at a center portion thereof; injecting an impurity to form an emitter at an upper portion of the first pillar; depositing a third polysilicon layer on the emitter, the third polysilicon layer being formed wider than the emitter; and forming self-aligned contact holes to form electrodes through the contact holes.

摘要翻译： 公开了具有双向工作特性并且其中基极的寄生结电容和其制造方法的柱状双极晶体管包括使用第一图案化绝缘层作为掩模蚀刻衬底以形成第一和第二柱 由其中的沟槽分隔开; 使用掩模注入杂质以在所述第一和第二柱下和所述第二柱中形成集电体; 在其上沉积第一氧化物层和第一多晶硅层; 使用第一氧化物层作为抛光停止器抛光第一多晶硅层; 去除所述第一多晶硅层的一部分和所述第一氧化物层的一部分以限定外部碱基; 将形成在第一柱的两侧上的氧化物层蚀刻到预定深度以限定连接部分并在其中形成掩埋多晶硅以形成连接部分; 在其上沉积第二氧化物层和第二多晶硅层; 使用第二氧化物层作为抛光停止器抛光第二多晶硅层; 仅去除在第一柱上方形成的第二氧化物层，以露出第一柱的表面; 在所述第一柱中注入杂质以在其中心部分形成基底; 注入杂质以在第一柱的上部形成发射极; 在发射极上沉积第三多晶硅层，第三多晶硅层形成得比发射极宽; 并且形成自对准接触孔，以通过接触孔形成电极。

公开(公告)号：US5289421A

公开(公告)日：1994-02-22

申请号：US665261

申请日：1991-03-05

申请人： Jin-Hyo Lee ,  Kyu-Hong Lee

发明人： Jin-Hyo Lee ,  Kyu-Hong Lee

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C11/4099 ,  H01L21/8229 ,  H01L27/102 ,  G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4099

摘要： A dynamic random access memory (DRAM) with low noise characteristics comprises a plurality of memory cells each consisting of a pair of reference memory cells respectively arranged between a word line and a pair of adjacent bit lines. The reference memory cells store signals of opposite levels corresponding to one bit of information. Each of the reference memory cells consists of a capacitor and switching transistor. One end of the capacitor is connected to the collector of the transistor. The other end of the capacitor is connected to one of the pair of bit lines adjacent thereto. The base of the transistor is connected to the word line, and the emitter of the transistor is completed to receive a reference voltage.

摘要翻译： 具有低噪声特性的动态随机存取存储器（DRAM）包括多个存储单元，每个存储单元由分别布置在字线和一对相邻位线之间的一对参考存储单元构成。 参考存储单元存储对应于一位信息的相反电平的信号。 每个参考存储单元由电容器和开关晶体管组成。 电容器的一端连接到晶体管的集电极。 电容器的另一端连接到与其相邻的一对位线之一。 晶体管的基极连接到字线，并且晶体管的发射极完成以接收参考电压。