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23 条记录 (耗时 0.02 秒)

    Sidewall strap
    1.
    发明授权
    Sidewall strap 失效
    侧壁带

    公开(公告)号：US5521118A

    公开(公告)日：1996-05-28

    申请号：US440574

    申请日：1995-05-15

    申请人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

    发明人： Chung H. Lam ,  James S. Nakos ,  Donald M. Kenney ,  Eric Adler

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

    CPC分类号： H01L27/10861 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90

    摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

    摘要翻译： 本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。 侧壁连接器具有包括外表面的顶部部分。 导电构件接触顶部，将轨道连接到导电区域或外部导体。 位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。 然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。 通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。 连接器用于形成用于DRAM单元的带子。

    Sidewall strap
    2.
    发明授权
    Sidewall strap 失效
    侧壁带

    公开(公告)号：US5691549A

    公开(公告)日：1997-11-25

    申请号：US720991

    申请日：1996-10-15

    申请人： Chung Hon Lam ,  James S. Nakos ,  Donald McAlpine Kenney ,  Eric Adler

    发明人： Chung Hon Lam ,  James S. Nakos ,  Donald McAlpine Kenney ,  Eric Adler

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/80 ,  H01L31/112

    CPC分类号： H01L27/10861 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90

    摘要： The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.

    摘要翻译： 本发明是提供连接至少两个导电区域的导电路径的侧壁连接器。 侧壁连接器具有包括表面的顶部部分。 导电构件接触顶部，将轨道连接到导电区域或外部导体。 位于导电区域上的蚀刻停止层可用于在定向蚀刻期间保护导电区域以形成侧壁连接器。 然后使用导电桥连接导电区域和导电侧壁导轨的暴露部分，导电桥延伸跨越蚀刻停止层的厚度。 通过该过程形成“T”连接器，从一对相交的侧壁开始，其中两个侧壁具有与其相交的不同高度的顶部边缘。 连接器用于形成用于DRAM单元的带子。

    Method of fabricating a capacitor having sidewall spacer protecting the dielectric layer
    3.
    发明授权
    Method of fabricating a capacitor having sidewall spacer protecting the dielectric layer 有权
    制造具有保护电介质层的侧壁间隔物的电容器的方法

    公开(公告)号：US06993814B2

    公开(公告)日：2006-02-07

    申请号：US10057185

    申请日：2002-01-25

    申请人： Eric Adler

    发明人： Eric Adler

    IPC分类号： H01G7/00

    CPC分类号： H01L28/55 ,  H01G4/08 ,  H01G4/228 ,  Y10S29/016 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49146

    摘要： A capacitor structure is fabricated by forming a bottom plate, forming a dielectric layer overlaying the bottom plate, and forming a top plate over the dielectric layer. In addition, at least one insulating sidewall spacer that protects the dielectric layer during processing is formed along the perimeter of the top plate and overlaying a portion of the dielectric layer.

    摘要翻译： 通过形成底板，形成覆盖底板的电介质层，并在电介质层上形成顶板来制造电容器结构。 此外，沿着顶板的周边形成保护加工过程中的电介质层的至少一个绝缘侧壁间隔物，并覆盖介电层的一部分。

    Non-continuous encapsulation layer for MIM capacitor
    4.
    发明授权
    Non-continuous encapsulation layer for MIM capacitor 有权
    MIM电容器的非连续封装层

    公开(公告)号：US07326987B2

    公开(公告)日：2008-02-05

    申请号：US10908491

    申请日：2005-05-13

    申请人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    发明人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    IPC分类号： H01L27/108

    CPC分类号： H01L28/57

    摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

    摘要翻译： 本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。 选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。 通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

    One-mask metal-insulator-metal capacitor and method for forming same
    6.
    发明授权
    One-mask metal-insulator-metal capacitor and method for forming same 失效
    单掩模金属 - 绝缘体 - 金属电容器及其形成方法

    公开(公告)号：US06750114B2

    公开(公告)日：2004-06-15

    申请号：US10179285

    申请日：2002-06-26

    申请人： Eric Adler ,  Anthony Kendall Stamper

    发明人： Eric Adler ,  Anthony Kendall Stamper

    IPC分类号： H01L2120

    CPC分类号： H01L28/55 ,  H01L23/5223 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

    摘要： A capacitor structure formed on an insulation layer includes a lower electrode formed on a surface of the insulation layer, a dielectric layer formed on a surface of the lower electrode, an upper electrode formed on a surface of the dielectric layer, a first spacer formed on a side portion of the upper electrode, and a second spacer formed on a side portion of the first spacer and a side portion of the lower electrode. This capacitor structure is formed by depositing a metal-insulator-metal capacitor stack on top of a via, masking and etching an upper electrode of the metal-insulator-metal capacitor stack, depositing and etching a first spacer on an edge surface of the upper electrode, defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer, depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode, and forming a wiring layer on a surface of the upper electrode and a surface of the second spacer. This capacitor structure provides a capacitor that is not prone to leakage down the capacitor sidewall and the corresponding method of manufacture provides a capacitor that is fabricated with increased efficiency (e.g., fewer mask steps).

    摘要翻译： 形成在绝缘层上的电容器结构包括形成在绝缘层的表面上的下电极，形成在下电极的表面上的电介质层，形成在电介质层的表面上的上电极， 上电极的侧部，以及形成在第一间隔件的侧部上的第二间隔件和下电极的侧部。 该电容器结构通过在通孔的顶部沉积金属 - 绝缘体 - 金属电容器叠层而形成，掩蔽和蚀刻金属 - 绝缘体 - 金属电容器堆叠的上部电极，沉积和蚀刻位于上部的边缘表面上的第一间隔物 电极，基于所述第一间隔物限定所述金属 - 绝缘体 - 金属电容器的下电极，在所述第一间隔物的表面上沉积和蚀刻第二间隔物和所述下电极的边缘，以及在所述第一间隔物的表面上形成布线层 上电极和第二间隔件的表面。 这种电容器结构提供了不容易在电容器侧壁下泄漏的电容器，并且相应的制造方法提供了以增加的效率（例如，更少的掩模步骤）制造的电容器。

    Method to increase the tuning voltage range of MOS varactors
    7.
    发明授权
    Method to increase the tuning voltage range of MOS varactors 有权

    公开(公告)号：US06667539B2

    公开(公告)日：2003-12-23

    申请号：US09683014

    申请日：2001-11-08

    申请人： Eric Adler

    发明人： Eric Adler

    IPC分类号： H01L2993

    CPC分类号： H01L29/94

    摘要： A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

    One-mask metal-insulator-metal capacitor and method for forming same
    8.
    发明授权
    One-mask metal-insulator-metal capacitor and method for forming same 失效
    单掩模金属 - 绝缘体 - 金属电容器及其形成方法

    公开(公告)号：US06452779B1

    公开(公告)日：2002-09-17

    申请号：US10063140

    申请日：2002-03-25

    申请人： Eric Adler ,  Anthony Kendall Stamper

    发明人： Eric Adler ,  Anthony Kendall Stamper

    IPC分类号： H01G4228

    CPC分类号： H01L28/55 ,  H01L23/5223 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

    摘要： A capacitor structure formed on an insulation layer includes a lower electrode formed on a surface of the insulation layer, a dielectric layer formed on a surface of the lower electrode, an upper electrode formed on a surface of the dielectric layer, a first spacer formed on a side portion of the upper electrode, and a second spacer formed on a side portion of the first spacer and a side portion of the lower electrode. This capacitor structure is formed by depositing a metal-insulator-metal capacitor stack on top of a via, masking and etching an upper electrode of the metal-insulator-metal capacitor stack, depositing and etching a first spacer on an edge surface of the upper electrode, defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer, depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode, and forming a wiring layer on a surface of the upper electrode and a surface of the second spacer. This capacitor structure provides a capacitor that is not prone to leakage down the capacitor sidewall and the corresponding method of manufacture provides a capacitor that is fabricated with increased efficiency (e.g., fewer mask steps).

    摘要翻译： 形成在绝缘层上的电容器结构包括形成在绝缘层的表面上的下电极，形成在下电极的表面上的电介质层，形成在电介质层的表面上的上电极， 上电极的侧部，以及形成在第一间隔件的侧部上的第二间隔件和下电极的侧部。 该电容器结构通过在通孔的顶部沉积金属 - 绝缘体 - 金属电容器叠层而形成，掩蔽和蚀刻金属 - 绝缘体 - 金属电容器堆叠的上部电极，沉积和蚀刻位于上部的边缘表面上的第一间隔物 电极，基于所述第一间隔物限定所述金属 - 绝缘体 - 金属电容器的下电极，在所述第一间隔物的表面上沉积和蚀刻第二间隔物和所述下电极的边缘，以及在所述第一间隔物的表面上形成布线层 上电极和第二间隔件的表面。 这种电容器结构提供了不容易在电容器侧壁下泄漏的电容器，并且相应的制造方法提供了以增加的效率（例如，更少的掩模步骤）制造的电容器。

    Dense multi-gated device design
    9.
    发明授权
    Dense multi-gated device design 失效
    密集的多门控设备设计

    公开(公告)号：US06433372B1

    公开(公告)日：2002-08-13

    申请号：US09527863

    申请日：2000-03-17

    申请人： Eric Adler ,  Kerry Bernstein ,  John J. Ellis-Monaghan ,  Jenifer E. Lary ,  Edward J. Nowak ,  Norman J. Rohrer

    发明人： Eric Adler ,  Kerry Bernstein ,  John J. Ellis-Monaghan ,  Jenifer E. Lary ,  Edward J. Nowak ,  Norman J. Rohrer

    IPC分类号： H01L2972

    CPC分类号： H01L29/66484

    摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.

    摘要翻译： 具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。 通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层 绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。