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8 条记录 (耗时 0.026 秒)

    Non-continuous encapsulation layer for MIM capacitor
    1.
    发明授权
    Non-continuous encapsulation layer for MIM capacitor 有权
    MIM电容器的非连续封装层

    公开(公告)号：US07326987B2

    公开(公告)日：2008-02-05

    申请号：US10908491

    申请日：2005-05-13

    申请人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    发明人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    IPC分类号： H01L27/108

    CPC分类号： H01L28/57

    摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

    摘要翻译： 本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。 选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。 通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

    Non-Continuous encapsulation layer for MIM capacitor
    2.
    发明授权
    Non-Continuous encapsulation layer for MIM capacitor 失效
    MIM电容器的非连续封装层

    公开(公告)号：US06913965B2

    公开(公告)日：2005-07-05

    申请号：US10709133

    申请日：2004-04-15

    申请人： Wagdi W. Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    发明人： Wagdi W. Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/57

    摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

    摘要翻译： 本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。 选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。 通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

    NON-CONTINUOUS ENCAPSULATION LAYER FOR MIM CAPACITOR
    3.
    发明申请
    NON-CONTINUOUS ENCAPSULATION LAYER FOR MIM CAPACITOR 有权
    MIM电容器的非连续封装层

    公开(公告)号：US20050189615A1

    公开(公告)日：2005-09-01

    申请号：US10908491

    申请日：2005-05-13

    申请人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara Waterhouse ,  Michael Zierak

    发明人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara Waterhouse ,  Michael Zierak

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/57

    摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

    摘要翻译： 本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。 选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。 通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

    VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES
    4.
    发明申请
    VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES 有权
    变化的设备的破坏电压的变化区域形成

    公开(公告)号：US20070275534A1

    公开(公告)日：2007-11-29

    申请号：US11839106

    申请日：2007-08-15

    申请人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

    发明人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

    IPC分类号： H01L21/331

    CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

    摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

    摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

    VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES
    5.
    发明申请
    VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES 失效
    变化的设备的破坏电压的变化区域形成

    公开(公告)号：US20060270203A1

    公开(公告)日：2006-11-30

    申请号：US10908884

    申请日：2005-05-31

    申请人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

    发明人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

    IPC分类号： H01L21/425

    CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

    摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

    摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

    Method of Base Formation in a Bicmos Process
    7.
    发明申请
    Method of Base Formation in a Bicmos Process 有权
    Bicmos工艺中基体形成的方法

    公开(公告)号：US20070207567A1

    公开(公告)日：2007-09-06

    申请号：US10599938

    申请日：2005-04-06

    申请人： Peter Geiss ,  Alvin Joseph ,  Qizhi Liu ,  Bradley Orner

    发明人： Peter Geiss ,  Alvin Joseph ,  Qizhi Liu ,  Bradley Orner

    IPC分类号： H01L21/04 ,  H01L29/73

    CPC分类号： H01L29/0804 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

    摘要： Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

    摘要翻译： 公开了一种双极互补金属氧化物半导体（BiCMOS）或NPN / PNP器件，其具有集电极，集电极之上的本征基极，与集电极相邻的浅沟槽隔离区，在本征基极之上的凸起的外部基极，T形发射极 在外部基极之上，邻近发射极的间隔物和通过间隔物与发射极分离的硅化物层。