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公开(公告)号：US20090142895A1
公开(公告)日：2009-06-04
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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公开(公告)号：US07745298B2
公开(公告)日：2010-06-29
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/336
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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3.发明授权Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same 失效防止两个相邻触点之间的空隙引起的短路的装置和具有该触点的装置的方法公开(公告)号：US06369430B1
公开(公告)日：2002-04-09
申请号：US09823310
申请日：2001-04-02
IPC分类号： H01L2976
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/7682 , H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.
摘要翻译： 非常靠近在一起的晶体管之间的绝缘层可能具有空隙。 当在这些紧密晶体管之间的这些区域中形成接触时，在空隙位置处形成接触孔。 这些空隙可以在靠近在一起的接触位置之间延伸，使得导电材料沉积到这些接触孔中可以充分地延伸到空隙中以短两个这样的接触。 在沉积导电材料之前，通过将衬垫放置在接触孔中来限制接触孔中的空隙尺寸来防止这种情况。 这限制了导电材料进入空隙。 这样可以防止这两个触点之间的不必要的导电路径的空隙处于非常接近的位置。 在沉积导电材料之前蚀刻接触孔的底部以去除衬垫。
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公开(公告)号：US07402472B2
公开(公告)日：2008-07-22
申请号：US11067257
申请日：2005-02-25
IPC分类号： H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译： 用氮化步骤和退火处理栅极电介质。 之后，进行另外的氮化步骤和退火。 第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。
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公开(公告)号：US07288458B2
公开(公告)日：2007-10-30
申请号：US11302770
申请日：2005-12-14
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
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6.发明授权Dual metal gate electrode semiconductor fabrication process and structure thereof 失效双金属栅电极半导体制造工艺及其结构公开(公告)号：US07074664B1
公开(公告)日：2006-07-11
申请号：US11092418
申请日：2005-03-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.
摘要翻译： 半导体制造工艺包括图案化覆盖栅极电介质的第一栅极电极层。 第二栅极电极层形成在第一栅极电极层和栅极电介质上。 去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。 可以形成第三栅极电极层，覆盖第一和第二栅电极层。 第一栅极电极层可以包括TiN并且主要驻留在PMOS区域上，而第二栅极电极层可以包括TaC或TaSiN并且主要覆盖NMOS区域。 去除第二栅极电极层的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层的暴露部分的情况下执行化学机械处理（CMP）。
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7.发明授权公开(公告)号：US07071038B2
公开(公告)日：2006-07-04
申请号：US10946938
申请日：2004-09-22
IPC分类号： H01L21/84
CPC分类号： H01L21/28185 , H01L21/3213 , H01L29/513 , H01L29/517 , Y10S438/977 , Y10S438/981
摘要： A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.
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公开(公告)号：US07030001B2
公开(公告)日：2006-04-18
申请号：US10827202
申请日：2004-04-19
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , B82Y10/00 , B82Y30/00 , C23C16/042 , H01L21/28079 , H01L29/495 , H01L29/4958 , H01L29/7833
摘要： One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
摘要翻译： 一个实施例在衬底上形成栅极电介质层，然后在其中将形成第一器件类型的栅极电介质层的部分上选择性地沉积第一金属层。 不同于第一金属层的第二金属层形成在将形成第二器件类型的栅极电介质层的暴露部分上。 第一和第二装置类型中的每一种将具有不同的功函数，因为每个将包括与栅极电介质直接接触的不同金属。 在一个实施例中，第一金属层的选择性沉积由ALD执行，并且使用抑制层，其选择性地形成在栅极电介质层上，使得第一金属层可以仅选择性地沉积在栅极的那些部分 未被抑制层覆盖的介电层。
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9.发明授权Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode 有权具有双金属氧化物栅极电介质和单金属栅电极的半导体工艺和集成电路公开(公告)号：US06897095B1
公开(公告)日：2005-05-24
申请号：US10843850
申请日：2004-05-12
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.
摘要翻译： 半导体制造工艺包括在第一和第二阱区域分别形成第一和第二晶体管，其中第一晶体管具有第一栅极电介质，而第二晶体管具有不同于第一栅极电介质的第二栅极电介质。 第一晶体管具有第一栅电极，第二晶体管具有第二栅电极。 第一和第二栅电极的组成相同。 第一栅极电介质和第二栅极电介质可以都包括高K电介质，例如氧化铪和氧化铝。 第一和第二栅电极都包括覆盖各个栅极电介质的栅极电极层。 栅电极层优选为TaSiN和TaC。 第一和第二栅电极都可以包括覆盖栅电极层的导电层。 在一个这样的实施例中，导电层可以包括多晶硅和钨。
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公开(公告)号：US06790719B1
公开(公告)日：2004-09-14
申请号：US10410043
申请日：2003-04-09
IPC分类号： H01L21337
CPC分类号： H01L21/823468 , H01L21/82345 , H01L21/823462
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.
摘要翻译： 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻来蚀刻N沟道栅极堆叠和P沟道栅极堆叠的一部分。 通过湿式蚀刻完成P沟道栅叠层的蚀刻。 湿蚀刻对栅极电介质和第二金属类型是非常选择的，使得N沟道晶体管不会通过完成P沟道栅极堆叠的蚀刻而受到不利影响。
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