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    Method for forming a split gate memory device
    1.
    发明授权
    Method for forming a split gate memory device 有权
    用于形成分离栅极存储器件的方法

    公开(公告)号：US07416945B1

    公开(公告)日：2008-08-26

    申请号：US11676403

    申请日：2007-02-19

    申请人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    发明人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

    摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

    摘要翻译： 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中除去在牺牲隔离物上形成的纳米团簇并保留其他纳米团簇。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

    METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE
    2.
    发明申请
    METHOD FOR FORMING A SPLIT GATE MEMORY DEVICE 有权
    形成分离栅存储器件的方法

    公开(公告)号：US20080199996A1

    公开(公告)日：2008-08-21

    申请号：US11676403

    申请日：2007-02-19

    申请人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    发明人： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Matthew T. Herrick ,  Narayanan C. Ramani ,  Robert F. Steimle

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521

    摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

    摘要翻译： 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中在牺牲隔离物上形成的纳米团簇被去除并且其它纳米团簇保留。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。

    Method of removing nanoclusters in a semiconductor device
    4.
    发明授权
    Method of removing nanoclusters in a semiconductor device 有权
    在半导体器件中去除纳米团簇的方法

    公开(公告)号：US07186616B2

    公开(公告)日：2007-03-06

    申请号：US11082094

    申请日：2005-03-16

    申请人： Rajesh A. Rao ,  Ramachandran Muralidhar ,  Robert F. Steimle

    发明人： Rajesh A. Rao ,  Ramachandran Muralidhar ,  Robert F. Steimle

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/42332 ,  H01L29/66825

    摘要： A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400–900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device at a temperature in a range of 400–900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanociusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.

    摘要翻译： 一种用于从半导体器件中去除纳米团簇的方法包括：在400-900摄氏度的温度范围内蚀刻绝缘层的选定部分，使还原气体在半导体器件上流动，并使包含卤素的气体流过半导体器件 在400-900摄氏度的温度范围内。 在另一种形式中，用于去除纳米团簇的方法包括将锗或氮注入到纳米过滤器中，使用干蚀刻工艺蚀刻绝缘层的选定部分，以及使用对绝缘选择性的湿蚀刻工艺去除纳米团簇层 层。

    Method of forming a nanocluster charge storage device
    5.
    发明授权
    Method of forming a nanocluster charge storage device 有权
    形成纳米团簇电荷存储装置的方法

    公开(公告)号：US07091130B1

    公开(公告)日：2006-08-15

    申请号：US10876820

    申请日：2004-06-25

    申请人： Rajesh A. Rao ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Gowrishankar L. Chindalore

    发明人： Rajesh A. Rao ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Gowrishankar L. Chindalore

    IPC分类号： H01I21/302

    CPC分类号： H01L27/11546 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42332

    摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.

    摘要翻译： 通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。 堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。 第二形成的含多晶硅的层从包含多个存储单元的区域中去除。 在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。 在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。 在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。 在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。 存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

    Semiconductor device with nanoclusters
    6.
    发明授权
    Semiconductor device with nanoclusters 有权
    具有纳米团簇的半导体器件

    公开(公告)号：US06958265B2

    公开(公告)日：2005-10-25

    申请号：US10663621

    申请日：2003-09-16

    申请人： Robert F. Steimle ,  Ramachandran Muralidhar ,  Wayne M. Paulson ,  Rajesh A. Rao ,  Bruce E. White, Jr. ,  Erwin J. Prinz

    发明人： Robert F. Steimle ,  Ramachandran Muralidhar ,  Wayne M. Paulson ,  Rajesh A. Rao ,  Bruce E. White, Jr. ,  Erwin J. Prinz

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/115 ,  H01L29/423

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

    摘要： A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

    摘要翻译： 用纳米团簇形成装置的方法。 该方法包括形成纳米团簇（例如硅纳米晶体）并在纳米簇上形成氧化阻挡层，以在随后形成器件的电介质期间抑制氧化剂氧化纳米团簇。 在形成电介质后，去除至少一部分氧化阻挡层。 在一个示例中，该器件是其中纳米团簇用作存储器的电荷存储晶体管的电荷存储位置的存储器。 在该实施例中，氧化阻挡层由于形成用于存储器的高压晶体管的栅极电介质而保护纳米团簇免受氧化剂的影响。

    Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices
    10.
    发明授权
    Method of forming an integrated circuit having nanocluster devices and non-nanocluster devices 有权
    形成具有纳米簇装置和非纳米团簇装置的集成电路的方法

    公开(公告)号：US07183159B2

    公开(公告)日：2007-02-27

    申请号：US11035913

    申请日：2005-01-14

    申请人： Rajesh A. Rao ,  Robert F. Steimle

    发明人： Rajesh A. Rao ,  Robert F. Steimle

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11546 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/105 ,  H01L27/11526 ,  H01L29/785 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/943

    摘要： An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. Formation of the gate oxides of the transistors is sequenced based upon the gate oxide thickness and function of the transistors. Thin gate oxides for at least one region of transistors are formed after the formation of gate oxides for the region including the transistors having the nanocluster layer.

    摘要翻译： 通过识别多个区域形成集成电路，每个区域具有在多个区域之间具有不同栅极氧化物厚度的晶体管。 一个区域包括具有纳米团簇层的晶体管，另一个区域包括用于逻辑功能的具有薄栅极氧化物的晶体管。 基于晶体管的栅极氧化物厚度和功能对晶体管的栅氧化物的形成进行排序。 在用于包括具有纳米团簇层的晶体管的区域的栅极氧化物的形成之后，形成晶体管的至少一个区域的薄栅氧化物。