公开(公告)号：US10096582B2

公开(公告)日：2018-10-09

申请号：US15205702

申请日：2016-07-08

申请人： Cisco Technology, Inc.

发明人： Paul L. Mantiply ,  Straty Argyrakis

IPC分类号： H05K7/10 ,  H01L25/18 ,  H02M3/158 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18 ,  H01L25/16 ,  H01L23/538 ,  H05K1/02 ,  H01L23/367 ,  H01L25/00 ,  H05K3/34 ,  H01L23/00

摘要： Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a substrate, an ASIC, and a voltage regulator module. The substrate includes a first side, a second side, and a vertical interconnect access (via) extending between the first side and the second side. The ASIC is mounted on the first side of the substrate in alignment with the via. The voltage regulator module is mounted on the second side of the substrate in alignment with the via so that the voltage regulator module is electrically coupled to the ASIC through the via.

公开(公告)号：US20180012879A1

公开(公告)日：2018-01-11

申请号：US15205702

申请日：2016-07-08

申请人： Cisco Technology, Inc.

发明人： Paul L. Mantiply ,  Straty Argyrakis

IPC分类号： H01L25/18 ,  H05K1/18 ,  H01L23/538 ,  H05K3/34 ,  H01L25/00 ,  H01L23/367 ,  H02M3/158 ,  H05K1/02 ,  H05K1/11 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/16 ,  H01L25/50 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102 ,  H02M3/158 ,  H05K1/0204 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K1/185 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10166 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734

摘要： Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a substrate, an ASIC, and a voltage regulator module. The substrate includes a first side, a second side, and a vertical interconnect access (via) extending between the first side and the second side. The ASIC is mounted on the first side of the substrate in alignment with the via. The voltage regulator module is mounted on the second side of the substrate in alignment with the via so that the voltage regulator module is electrically coupled to the ASIC through the via.