公开(公告)号：US5561622A

公开(公告)日：1996-10-01

申请号：US120993

申请日：1993-09-13

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： G11C5/00 ,  H01L25/065 ,  G11C5/06 ,  H01L23/02

CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

公开(公告)号：US5502333A

公开(公告)日：1996-03-26

申请号：US220086

申请日：1994-03-30

申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Wayne J. Howell

发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Wayne J. Howell

IPC分类号： H01L21/66 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/02

CPC分类号： H01L24/49 ,  G11C29/808 ,  H01L22/22 ,  H01L23/5382 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19107

摘要： Electronic semiconductor structures utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.

摘要翻译： 电子半导体结构利用并入多芯片封装的电可编程备用电路。 多芯片封装中的可编程保护功能可以在有或没有包含备用芯片的情况下完成。 利用备用存储器电路，在封装和老化测试之后，堆叠的半导体芯片中的单个故障存储器单元可以在功能上被备用存储器电路的存储单元替代。 使用备用芯片，在封装和老化测试之后可能会发生非易失性保护，而无需线接合连接的物理重新布线。 因此，提出了替代电子半导体结构的具体细节，以及制造和备用方法。

公开(公告)号：US06233184B1

公开(公告)日：2001-05-15

申请号：US09191954

申请日：1998-11-13

申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

IPC分类号： G11C2900

CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

公开(公告)号：US5502667A

公开(公告)日：1996-03-26

申请号：US120876

申请日：1993-09-13

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard K. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard K. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： H01L25/18 ,  G11C5/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  G11C5/02

CPC分类号： G11C5/06 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C5/04 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/85207 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19107

摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成多芯片存储器模块结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得以更高级别的存储器芯片的外观定义更强大的存储器架构。 形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得在模块的I / O引脚上出现具有NxM存储器件的单个存储器芯片架构。 在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与包括该子单元的存储器芯片电互连。 控制逻辑芯片的尺寸小于包含子单元的存储器芯片的尺寸。 具有延伸穿过其中的内部开口的引线框固定到电接口层，并且控制逻辑芯片固定到电接口层以便驻留在引线框架内，从而产生致密的多芯片集成电路封装。 相应的制造技术包括促进存储器子单元的侧表面上的金属化图案化的方法。

公开(公告)号：US06426904B2

公开(公告)日：2002-07-30

申请号：US09803500

申请日：2001-03-09

申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

IPC分类号： G11C2900

CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

公开(公告)号：US5563086A

公开(公告)日：1996-10-08

申请号：US406284

申请日：1995-03-17

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： G11C5/00 ,  H01L25/065 ,  H01L21/70

CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

公开(公告)号：US06574763B1

公开(公告)日：2003-06-03

申请号：US09473886

申请日：1999-12-28

申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

IPC分类号： G01R3128

CPC分类号： G01R31/287

摘要： A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.

摘要翻译： 为具有冗余位和可寻址存储位置的存储器阵列提供老化过程。 老化过程包括以下步骤：将存储器阵列的温度升高到预定温度，测试阵列中的所有位，检测故障位和可操作位，用冗余的可操作位代替故障位，校正在 阵列原位，并将存储器阵列的温度降低到环境温度以完成老化过程。 提供了一种用于执行上述处理的装置，其包括用于生成测试图案并将测试图案应用于存储器阵列的测试电路，以便测试存储器阵列内的所有位。 耦合到测试电路并且适于耦合到存储器阵列的比较电路将存储器阵列的实际响应和预期响应与测试模式进行比较，并基于此检测故障和可操作的位。 耦合到比较电路和测试电路的故障地址缓冲寄存器存储具有错误位的每个可寻址存储位置的地址。 冗余控制逻辑耦合到故障地址缓冲寄存器并适于耦合到存储器阵列，读出由故障地址缓冲寄存器存储的每个地址，并用冗余可操作位替换每个故障位。

公开(公告)号：US06812122B2

公开(公告)日：2004-11-02

申请号：US10095889

申请日：2002-03-12

申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

IPC分类号： H01L2144

CPC分类号： H01L21/763 ,  H01L23/5252 ,  H01L27/10861 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.

摘要翻译： 用于形成第一导电类型的半导体衬底中的第一次电压可编程逻辑元件的方法，在所述衬底的表面下方形成第一层，所述第一层具有第二导电类型。 沟槽通过表面形成并穿过第一层。 沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。 第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。

公开(公告)号：US06567950B1

公开(公告)日：2003-05-20

申请号：US09302917

申请日：1999-04-30

申请人： Claude L. Bertin ,  Timothy J. Dell ,  Erik L. Hedberg

发明人： Claude L. Bertin ,  Timothy J. Dell ,  Erik L. Hedberg

IPC分类号： G11C2900

CPC分类号： G11C29/70 ,  G11C29/838

摘要： An improved chip sparing system and method of operation are provided in which a failed chip is detected even if there are multiple errors on a single chip and one or more spare chips are provided within the system; and in which spare chips or space chip I/Os are dynamically inserted into the system upon detection of a failed chip or chip I/O without the necessity of shutting down and rebooting the system or even without the necessity of re-initializing the memory.

摘要翻译： 提供了一种改进的芯片保存系统和操作方法，其中即使在单个芯片上存在多个错误并且在系统内提供一个或多个备用芯片，也检测到故障芯片; 并且在检测到故障的芯片或芯片I / O时，备用芯片或空芯片I / O被动态地插入到系统中，而不需要关闭和重新启动系统，或者甚至不需要重新初始化存储器。

公开(公告)号：US06297531B2

公开(公告)日：2001-10-02

申请号：US09002399

申请日：1998-01-05

申请人： Michael D. Armacost ,  Claude L. Bertin ,  Erik L. Hedberg ,  Jack A. Mandelman

发明人： Michael D. Armacost ,  Claude L. Bertin ,  Erik L. Hedberg ,  Jack A. Mandelman

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203 ,  Y10S257/903

摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.

摘要翻译： 可以是N型FET（NFET）或P型FET（PFET）的垂直场效应晶体管（FET）; 可以是两个或更多个NFET或两个或更多个PFETS的多器件垂直结构; 逻辑门包括至少一个垂直FET或至少一个多器件垂直; 包括至少一个垂直FET的静态随机存取存储器（SRAM）单元和阵列; 包括至少一个这样的SRAM单元的存储器阵列; 以及形成垂直FET结构的过程，垂直多器件（multi-FET）结构，逻辑门和SRAM单元。 垂直FET是NPN或PNP的外延生长层叠堆叠，其中多晶硅栅极层的侧面与器件的沟道层相邻。 多FET结构可以通过形成与相同沟道层相邻的两个或多个栅极的侧面，或者通过在相同的堆叠中形成多个通道层，例如PNPNP或NPNPN，每个具有其自己的栅极，即侧面 的多晶硅栅极层。 SRAM单元可以通过选择性地增厚栅极层而辐射硬化，以增加存储节点电容，提供高电阻电池布线或者通过包括NO或ONO的多层栅极氧化物层或其任何组合。