摘要:
A non-volatile latch circuit is provided. The non-volatile latch circuit includes a nanotube switching element capable of switching between resistance states and non-volatilely retaining the resistance state. The non-volatile latch circuit includes a volatile latch circuit is capable of receiving and volatilely storing a logic state. When the nanotube switching element is a resistance state, the volatile latch circuit retains a corresponding logic state and outputs that corresponding logic state at an output terminal. A non-volatile register file configuration circuit for use with a plurality of non-volatile register files is also provided. The non-volatile register file configuration circuit includes a selection circuitry and a plurality of nanotube fuse elements, each in electrical communication with one of a plurality of non-volatile register files. The selection circuitry is capable of applying electrical stimulus to each of the selected nanotube fuse elements to selectively bypass the corresponding register file.
摘要:
A non-volatile resistive memory is provided. The memory includes at least one non-volatile memory cell and selection circuitry. Each memory cell has a two-terminal nanotube switching device having and a nanotube fabric article disposed between and in electrical communication with two conductive terminals. Selection circuitry is operable to select the two-terminal nanotube switching device for read and write operations. Write control circuitry, responsive to a control signal, supplies write signals to a selected memory cell to induce a change in the resistance of the nanotube fabric article, the resistance corresponding to an informational state of the memory cell. Resistance sensing circuitry in communication with a selected nonvolatile memory cell, senses the resistance of the nanotube fabric article and provides the control signal to the write control circuitry. Read circuitry reads the corresponding informational state of the memory cell.
摘要:
Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.
摘要:
Under one aspect, a nonvolatile nanotube diode includes: a substrate; a semiconductor element disposed over the substrate, the semiconductor element having an anode and a cathode and capable of forming an electrically conductive pathway between the anode and the cathode; a nanotube switching element disposed over the semiconductor element, the nanotube switching element including a conductive contact and a nanotube fabric element capable of a plurality of resistance states; and a conductive terminal disposed in spaced relation to the conductive contact, wherein the nanotube fabric element is interposed between and in electrical communication with the conductive contact and the conductive contact is in electrical communication with the cathode, and wherein in response to electrical stimuli applied to the anode and the conductive terminal, the nonvolatile nanotube diode is capable of forming an electrically conductive pathway between the anode and the conductive terminal.
摘要:
Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell.
摘要:
Under one aspect, a method of making a nanotube switch includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube fabric over the first conductive terminal; and depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals. In some embodiments, the first and second conductive terminals and the multilayer nanotube fabric are lithographically patterned so as to each have substantially the same lateral dimensions, e.g., to each have a substantially circular or rectangular lateral shape. In some embodiments, the multilayer nanotube fabric has a thickness from 10 nm to 200 nm, e.g., 10 nm to 50 nm. The structure may include an addressable diode provided under the first conductive terminal or deposited over the second terminal.
摘要:
Under one aspect, a non-volatile nanotube switch includes a first terminal; a nanotube block including a multilayer nanotube fabric, at least a portion of which is positioned over and in contact with at least a portion of the first terminal; a second terminal, at least a portion of which is positioned over and in contact with at least a portion of the nanotube block, wherein the nanotube block is constructed and arranged to prevent direct physical and electrical contact between the first and second terminals; and control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube block can switch between a plurality of electronic states in response to a plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube block provides an electrical pathway of different resistance between the first and second terminals.
摘要:
A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.
摘要:
Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.
摘要:
Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.