公开(公告)号：US6130472A

公开(公告)日：2000-10-10

申请号：US122353

申请日：1998-07-24

申请人： Claudius Feger ,  John Patrick Hummel

发明人： Claudius Feger ,  John Patrick Hummel

IPC分类号： H01L21/60 ,  H01L21/312 ,  H01L23/00 ,  H01L29/40

CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044

摘要： The present invention provides polymeric materials that can be used as a moisture/ion barrier layer for inhibiting the penetration of moisture and/or ions for coming into contact with the metal wiring found in chip level interconnects. The present invention also provides a means to protect the chip backside from being contaminated by metal atoms or metal ions which are capable of forming mobile silicides, which can migrate to the active sites of the semiconductor and destroy them. The present invention further provides methods of forming such polymeric barrier layers on at least one surface of an interconnect structure.

公开(公告)号：US06423566B1

公开(公告)日：2002-07-23

申请号：US09629264

申请日：2000-07-31

申请人： Claudius Feger ,  John Patrick Hummel

发明人： Claudius Feger ,  John Patrick Hummel

IPC分类号： H01L2100

CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

摘要： The present invention provides polymeric materials that can be used as a moisture/ion barrier layer for inhibiting the penetration of moisture and/or ions for coming into contact with the metal wiring found in chip level interconnects. The present invention also provides a means to protect the chip backside from being contaminated by metal atoms or metal ions which are capable of forming mobile silicides, which can migrate to the active sites of the semiconductor and destroy them. The present invention further provides methods of forming such polymeric barrier layers on at least one surface of an interconnect structure.

摘要翻译： 本发明提供了可用作水分/离子阻挡层的聚合物材料，用于抑制水分和/或离子渗透与芯片级互连中发现的金属布线接触。 本发明还提供了一种保护芯片背面免受金属原子或金属离子污染的手段，金属原子或金属离子能够形成可移动的硅化物，其可以迁移到半导体的活性位置并破坏它们。 本发明还提供了在互连结构的至少一个表面上形成这种聚合物阻挡层的方法。

公开(公告)号：US06448176B1

公开(公告)日：2002-09-10

申请号：US09699900

申请日：2000-10-30

申请人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063 ,  Y10S438/945

摘要： The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

摘要翻译： 本发明涉及用于在衬底中形成双浮雕图案的平版印刷方法，以及通过双镶嵌工艺制造半导体芯片中的多层互连结构的方法，其中形成在电介质中的双浮雕空穴填充有导电材料 形成布线和通孔层。 本发明包括通过添加易于整合的侧壁衬里而修改的两次图案化单掩膜层双镶嵌工艺，以保护有机层间和层间电介质免受光刻胶剥离步骤在光刻返工期间引起的潜在损伤。 本发明还包括一种用于形成双重图案硬掩模的方法，该双面图案硬掩模可用于形成用于双镶嵌处理​​的双浮雕空腔，所述双图案硬掩模包括具有第一图案的一层或多层第一组和 具有第二图案的第二组一层或多层。

公开(公告)号：US6140226A

公开(公告)日：2000-10-31

申请号：US126212

申请日：1998-07-30

申请人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063 ,  Y10S438/945

摘要： The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

公开(公告)号：US5976710A

公开(公告)日：1999-11-02

申请号：US838757

申请日：1997-04-10

申请人： Krishna Gandhi Sachdev ,  John Patrick Hummel ,  Sundar Mangalore Kamath ,  Robert Neal Lang ,  Anton Nendaic ,  Charles Hampton Perry ,  Harbans Sachdev

发明人： Krishna Gandhi Sachdev ,  John Patrick Hummel ,  Sundar Mangalore Kamath ,  Robert Neal Lang ,  Anton Nendaic ,  Charles Hampton Perry ,  Harbans Sachdev

IPC分类号： C08G73/10 ,  H01L23/12 ,  H01L23/14 ,  H01L23/498 ,  H01L23/52 ,  H01L23/532 ,  H01L23/538 ,  H01L29/12

CPC分类号： H01L23/49894 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10T428/12528 ,  Y10T428/12549 ,  Y10T428/12569 ,  Y10T428/12632 ,  Y10T428/31681 ,  Y10T428/31721

摘要： A multilevel high density interconnect structure of a semiconductor device or package including a substrate having at least one conductive feature therein, a film of a polyimide composition on the substrate and selected from the group consisting of a cured product of a polyamic acid and a cured product of a polyamic ester. The polyamic acid is prepared by reacting a stoichiometric excess of a linear aromatic diamine and aromatic dianhydride to form a first reaction product where the molar ratio of said diamine to said aromatic anhydride is in the range from 100:97 to 100:99.5 and then reacting the first reaction product with an aromatic anhydride. The polyamic ester is prepared by reacting a stoichiometric excess of a linear aromatic diamine and an aromatic diester diacyl chloride to form a second reaction product where the molar ratio of said diamine to said diester diacyl chloride is in the range from 100:97 to 100:99.5 and then reacting the second reaction product with aromatic anhydride. There is at least one interconnective conductive metallurgical feature in the film a polyimide composition in contact with said conductive feature in said substrate.

摘要翻译： 一种半导体器件或封装的多层高密度互连结构，其包括其中具有至少一个导电特征的衬底，所述衬底上的聚酰亚胺组合物的膜选自聚酰胺酸和固化产物的固化产物 的聚酰胺酯。 聚酰胺酸通过使化学计量过量的线性芳族二胺和芳族二酸酐反应以形成第一反应产物，其中所述二胺与所述芳族酸酐的摩尔比在100:97至100:99.5的范围内，然后使 第一反应产物与芳族酸酐反应。 通过使化学计量过量的线性芳族二胺和芳族二酯二酰氯反应形成第二反应产物，其中所述二胺与所述二酯二酰氯的摩尔比为100：97至100： 99.5，然后使第二反应产物与芳族酸酐反应。 在膜中存在与所述衬底中的所述导电特征接触的聚酰亚胺组合物中的至少一个互连导电冶金特征。

公开(公告)号：US5962113A

公开(公告)日：1999-10-05

申请号：US739144

申请日：1996-10-28

申请人： Hugh Ralph Brown ,  Kenneth Raymond Carter ,  Hyuk-Jin Cha ,  Richard Anthony Dipietro ,  James Lupton Hedrick ,  John Patrick Hummel ,  Robert Dennis Miller ,  Do Yeung Yoon

发明人： Hugh Ralph Brown ,  Kenneth Raymond Carter ,  Hyuk-Jin Cha ,  Richard Anthony Dipietro ,  James Lupton Hedrick ,  John Patrick Hummel ,  Robert Dennis Miller ,  Do Yeung Yoon

IPC分类号： C08G77/455 ,  C08G73/10 ,  C09D183/10 ,  H01L21/316 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  B32B3/10 ,  B32B15/08

CPC分类号： H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/31681 ,  Y10T428/31721

摘要： The invention relates to an integrated circuit device comprising (i) a substrate; (ii) metallic circuit lines positioned on the substrate and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises the reaction product of an organic polysilica and polyamic ester preferably terminated with an alkoxysilyl alkyl group.

摘要翻译： 本发明涉及一种集成电路器件，包括：（i）衬底; （ii）位于基板上的金属电路线，和（iii）位于电路线上的电介质材料。 电介质材料包括有机聚硅氧烷与优选用烷氧基甲硅烷基烷基封端的聚酰胺酯的反应产物。