公开(公告)号：US11688811B2

公开(公告)日：2023-06-27

申请号：US17123231

申请日：2020-12-16

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Emmanuel Augendre ,  Maxime Argoud ,  Sylvain Maitrejean ,  Pierre Morin ,  Raluca Tiron

IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L27/12

CPC分类号： H01L29/78696 ,  H01L27/127 ,  H01L27/1222 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/78654

摘要： A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

公开(公告)号：US10600786B2

公开(公告)日：2020-03-24

申请号：US15452049

申请日：2017-03-07

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

发明人： Sylvain Maitrejean ,  Emmanuel Augendre ,  Pierre Morin ,  Shay Reboh

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/266 ,  H01L21/268 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66

摘要： Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.

公开(公告)号：US09460971B2

公开(公告)日：2016-10-04

申请号：US14955801

申请日：2015-12-01

申请人： STMICROELECTRONICS, INC. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Nicolas Loubet ,  Sylvain Maitrejean ,  Romain Wacquez

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/266 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/845 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849

摘要： Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

公开(公告)号：US20170076944A1

公开(公告)日：2017-03-16

申请号：US15260767

申请日：2016-09-09

申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS

发明人： Emmanuel AUGENDRE ,  Aomar Halimaoui ,  Sylvain Maitrejean ,  Shay Reboh

IPC分类号： H01L21/02 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/165 ,  H01L21/265 ,  H01L29/10

CPC分类号： H01L21/02694 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78687

摘要： A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s) d) performing recrystallisation of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).

公开(公告)号：US09536951B2

公开(公告)日：2017-01-03

申请号：US14849060

申请日：2015-09-09

申请人： Commissariat a l'Energie Atomique et aux Energies Alternatives

发明人： Sylvain Maitrejean ,  Emmanuel Augendre ,  Louis Hutin ,  Yves Morand

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/7853

摘要： FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.

摘要翻译： FinFET晶体管至少包括：形成沟道的一个鳍，源极和漏极，包括富硅SiGe的第一部分和电介质或半导体材料的第二部分的交替堆叠，以及富含锗的SiGe的第三部分 至少布置在所述第一部分的侧面上，一个栅极覆盖所述通道，并且其中所述第三部分中的每一个包括被所述栅极覆盖的晶体取向[111]的面。

公开(公告)号：US11694991B2

公开(公告)日：2023-07-04

申请号：US17304664

申请日：2021-06-24

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Frank Fournel ,  Emilie Bourjot ,  Séverine Cheramy ,  Sylvain Maitrejean ,  Loic Sanchez

IPC分类号： H01L21/683 ,  H01L23/00 ,  B32B38/00 ,  B32B38/18 ,  H01L21/67

CPC分类号： H01L24/97 ,  B32B38/00 ,  B32B38/18 ,  H01L21/67144 ,  H01L21/6836 ,  H01L2224/95085 ,  H01L2224/97

摘要： A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.

公开(公告)号：US10978594B2

公开(公告)日：2021-04-13

申请号：US14978778

申请日：2015-12-22

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Emmanuel Augendre ,  Maxime Argoud ,  Sylvain Maitrejean ,  Pierre Morin ,  Raluca Tiron

IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L27/12

摘要： The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.

公开(公告)号：US09853130B2

公开(公告)日：2017-12-26

申请号：US15049468

申请日：2016-02-22

申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives

发明人： Sylvain Maitrejean ,  Emmanuel Augendre ,  Jean-Charles Barbe ,  Benoit Mathieu ,  Yves Morand

IPC分类号： H01L21/469 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/6681 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/78696

摘要： A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting elements, the method including providing on a substrate at least one first semiconducting structure formed from a semiconducting stack including alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first material; then removing portions of the second material from the first semiconducting structure by selective etching, the removed portions forming at least one empty space; filling the empty space with a dielectric material; forming a straining zone on the first semiconducting structure based on a first strained material having an intrinsic strain; and performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the first material.

公开(公告)号：US09853124B2

公开(公告)日：2017-12-26

申请号：US15352198

申请日：2016-11-15

申请人： Commissariat a L'Energie Atomique et aux Energies Alternatives

发明人： Sylvain Barraud ,  Emmanuel Augendre ,  Sylvain Maitrejean ,  Nicolas Posseme

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/324 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06

CPC分类号： H01L29/66553 ,  H01L21/02667 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.

公开(公告)号：US11810789B2

公开(公告)日：2023-11-07

申请号：US16709993

申请日：2019-12-11

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Shay Reboh ,  Victor Boureau ,  Sylvain Maitrejean ,  Francois Andrieu

IPC分类号： H01L21/308 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L21/3083 ,  H01L21/0245 ,  H01L21/02249 ,  H01L21/3081 ,  H01L21/8234

摘要： A method for producing a semiconductor substrate is provided, including: producing a superficial layer arranged on a buried dielectric layer and including a strained semiconductor region; producing an etching mask on the superficial layer, covering a part of the region; etching the superficial layer to a pattern of the mask, exposing a first lateral edge of a first strained semiconductor portion belonging to the part and contacting the dielectric layer; forming a mechanical barrier from a second portion of material belonging to the first portion, the second portion having a bottom surface contacting the dielectric layer and an upper surface contacting the mask, the barrier arranged against the part and bearing mechanically against the second portion, and removing the mask.