公开(公告)号：US07132336B1

公开(公告)日：2006-11-07

申请号：US10123263

申请日：2002-04-15

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

IPC: H01L21/336

CPC classification number: H01L29/513 ,  H01L21/265 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/78

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

Abstract translation: 公开了一种改进的半导体存储器结构及其制造方法。 存储器结构包括具有形成在沟道区上的电介质区域的半导体衬底。 在电介质区域的顶部和底部之间形成掺杂区域。 该掺杂区域包括合适的电子亲和性材料。 栅电极与电介质区域的顶部连接。 在一些实施方案中，使用注入技术将合适的电子亲和性材料引入掺杂区域。 在另一个实施方案中，使用电介质区域的等离子体处理和在介电区域和掺杂区域的顶部上再沉积附加电介质材料将电子亲和性材料引入掺杂区域。

公开(公告)号：US06822308B2

公开(公告)日：2004-11-23

申请号：US10600665

申请日：2003-06-20

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: H01L2900

CPC classification number: H01L21/306 ,  H01L21/31

Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

Abstract translation: 公开了一种化学改变硅表面和相关介电材料的方法。

公开(公告)号：US06649219B2

公开(公告)日：2003-11-18

申请号：US09792691

申请日：2001-02-23

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: C23C1640

CPC classification number: H01L21/02126 ,  C01B33/126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  Y02P20/129

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom. Also provided is a low dielectric constant fluorine and carbon-doped silicon oxide dielectric material for use in an integrated circuit structure which contains: silicon atoms bonded to oxygen atoms; silicon atoms bonded to carbon atoms; and carbon atoms bonded to fluorine atoms; where the dielectric material also has a characteristic selected from: (a) the presence of at least one C—C bond; (b) the presence of at least one carbon atom bonded to from 1 to 2 fluorine atoms; and (c) the presence of at least one silicon atom bonded to from 0 to 2 oxygen atoms.

公开(公告)号：US06627556B1

公开(公告)日：2003-09-30

申请号：US10131431

申请日：2002-04-24

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: H01L21302

CPC classification number: H01L21/306 ,  H01L21/31

Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

公开(公告)号：US06566262B1

公开(公告)日：2003-05-20

申请号：US10004461

申请日：2001-11-01

Applicant: Paul Rissman ,  Richard Schinella ,  Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Paul Rissman ,  Richard Schinella ,  Sheldon Aronowitz ,  Vladimir Zubkov

IPC: H01L2144

CPC classification number: H01L23/53238 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer. In another method embodiment for forming a capping layer on a copper-containing conducting structure, a substrate having formed thereon electrically conducting layer comprised of a copper-containing material is provided. A layer of reactive material is then formed on the surface of the substrate. This is followed by reacting a portion of the layer of reactive material with the copper-containing material of the conducting layer to form an alloy material on the conducting layer. Unalloyed reactive material is removed from the substrate by heating the substrate to a temperature where the unalloyed reactive material desorbs from the surface of the substrate but where the alloy material remains in place on the substrate surface thereby forming a self-aligned capping layer. In another embodiment, the process is repeated iteratively until a capping layer having the desired thickness is formed.

Abstract translation: 本发明的实施方案包括在含铜层上形成的合金材料的覆盖层，该合金构造成防止铜通过覆盖层的扩散。 在另一个实施例中，合金覆盖层与下面的导电层自对准。 具体实施方案包括由铜的合金与包括但不限于钙，锶，钡和其它碱土金属的材料形成的封盖层，以及来自其它基团的材料，例如镉或硒。 本发明还包括在含铜导电结构上形成合金覆盖层的方法。 一种这样的方法包括提供其上形成有由含铜材料构成的导电层并在导电层上形成合金覆盖层的衬底。 在另一方法实施例中，形成合金覆盖层包括在导电层上形成自对准覆盖层。在用于在含铜导电结构上形成覆盖层的另一方法实施例中，其上形成有导电层的基板包括 提供含铜材料。 然后在衬底的表面上形成一层反应性材料。 然后使反应性材料层的一部分与导电层的含铜材料反应，以在导电层上形成合金材料。 通过将衬底加热到​​非合金反应物质从衬底表面脱附的温度，但是合金材料保留在衬底表面上的适当位置，从而形成非对准的覆盖层，从衬底去除非合金反应性材料。 在另一个实施方案中，迭代地重复该过程，直到形成具有所需厚度的覆盖层。

公开(公告)号：US20050179138A1

公开(公告)日：2005-08-18

申请号：US11104763

申请日：2005-04-12

Applicant: Vladimir Zubkov ,  Sheldon Aronowitz

Inventor： Vladimir Zubkov ,  Sheldon Aronowitz

IPC: H01L21/44 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L21/76831 ,  H01L21/76802

Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

Abstract translation: 提供了一种用于半导体器件的阻挡层。 该半导体器件包括电介质层，导电含铜层和将电介质层与含铜层隔开的阻挡层。 阻挡层包括氧化硅层和掺杂剂，其中掺杂剂是二价离子，其掺杂与含铜层相邻的氧化硅层。 提供形成阻挡层的方法。 提供具有表面的氧化硅层。 氧化硅层的表面掺杂有二价离子以形成延伸到氧化硅层的表面的势垒层。 在阻挡层的表面上形成导电含铜层，其中阻挡层防止铜扩散到衬底中。

公开(公告)号：US20050098856A1

公开(公告)日：2005-05-12

申请号：US10652007

申请日：2003-08-29

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: C01B33/12 ,  C23C16/40 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/31 ,  H01L23/58

CPC classification number: H01L21/02126 ,  C01B33/126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  Y02P20/129

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom. Also provided is a low dielectric constant fluorine and carbon-doped silicon oxide dielectric material for use in an integrated circuit structure which contains: silicon atoms bonded to oxygen atoms; silicon atoms bonded to carbon atoms; and carbon atoms bonded to fluorine atoms; where the dielectric material also has a characteristic selected from: (a) the presence of at least one C—C bond; (b) the presence of at least one carbon atom bonded to from 1 to 2 fluorine atoms; and (c) the presence of at least one silicon atom bonded to from 0 to 2 oxygen atoms.

公开(公告)号：US06572925B2

公开(公告)日：2003-06-03

申请号：US09792683

申请日：2001-02-23

Applicant: Vladimir Zubkov ,  Sheldon Aronowitz

Inventor： Vladimir Zubkov ,  Sheldon Aronowitz

IPC: C23C1640

CPC classification number: H01L21/02131 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31629

Abstract: A process is provided for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes including one or more organofluoro silanes characterized by the absence of aliphatic C—H bonds. In one embodiment, the process is carried out using a mild oxidizing agent. Also provided is a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material for use in an integrated circuit structure containing silicon atoms bonded to oxygen atoms, silicon atoms bonded to carbon atoms, and carbon atoms bonded to fluorine atoms, where the dielectric material is characterized by the absence of aliphatic C—H bonds and where the dielectric material has a ratio of carbon atoms to silicon atoms of C:Si greater than about 1:3.

Abstract translation: 提供一种通过与氧化剂反应形成低k含氟和碳的氧化硅介电材料的方法，所述氧化剂包括一种或多种包含一种或多种以不存在脂族C-H键的有机氟硅烷的硅烷。 在一个实施方案中，该方法使用温和的氧化剂进行。 还提供了一种用于集成电路结构的低介电常数含氟和含碳氧化硅电介质材料，该集成电路结构包含与氧原子键合的硅原子，与碳原子键合的硅原子和与氟原子键合的碳原子，其中电介质材料 其特征在于不存在脂族CH键，并且其中介电材料具有大于约1:3的C：Si的碳原子与硅原子的比例。

公开(公告)号：US07081296B2

公开(公告)日：2006-07-25

申请号：US10804980

申请日：2004-03-16

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Richard Schinella

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Richard Schinella

IPC: C23C16/00

CPC classification number: C23C16/45525 ,  C23C16/455 ,  C23C16/45527 ,  C23C16/463 ,  H01L21/3141 ,  Y10T428/265

Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.

Abstract translation: 提供了一种在衬底上形成层的方法。 通常，在衬底上沉积一层第一反应性物质。 第一反应性物质的层与第二反应性物质反应以产生第一产物。 未反应的反应物质优先解吸，留下第一产物的一层。

公开(公告)号：US06989565B1

公开(公告)日：2006-01-24

申请号：US10698169

申请日：2003-10-31

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace S. Sun

IPC: H01L29/792

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/78

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

Abstract translation: 公开了一种改进的半导体存储器结构及其制造方法。 存储器结构包括具有在半导体衬底的沟道区上形成的电介质叠层的半导体衬底。 电介质堆叠包括作为存储器件的电荷存储中心工作的电子俘获材料层。 栅电极与电介质叠层的顶部连接。 在各种实施例中，电子捕获材料形成介电叠层的更大或更小部分。 本发明包括用于形成这种存储器件的方法实施例。