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1.发明授权Method of forming an interconnect structure diffusion barrier with high nitrogen content 有权形成具有高氮含量的互连结构扩散阻挡层的方法公开(公告)号：US07378338B2
公开(公告)日：2008-05-27
申请号：US11461220
申请日：2006-07-31
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.
摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。
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公开(公告)号：US07098537B2
公开(公告)日：2006-08-29
申请号：US10707117
申请日：2003-11-21
CPC分类号： H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.
摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。
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3.发明授权公开(公告)号：US06943097B2
公开(公告)日：2005-09-13
申请号：US10643534
申请日：2003-08-19
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L29/49
CPC分类号： H01L21/28088 , H01L21/28562 , H01L21/32053 , H01L21/76841 , H01L29/4966 , H01L2221/1078
摘要： The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.
摘要翻译： 本发明通过利用原子层沉积（ALD）提供含有IVB族或VB族金属，硅和任选的氮的金属膜。 特别地，本发明提供形成金属硅化物的低温热ALD方法和形成金属氮化硅膜的等离子体增强原子层沉积（PE-ALD）方法。 本发明的方法能够在基材的表面上形成厚度为单层或更薄的金属膜。 本发明中提供的金属膜可用于接触金属化，金属栅极或扩散阻挡层。
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4.发明授权公开(公告)号：US07998842B2
公开(公告)日：2011-08-16
申请号：US11214211
申请日：2005-08-29
IPC分类号： H01L21/285
CPC分类号： H01L21/28088 , H01L21/28562 , H01L21/32053 , H01L21/76841 , H01L29/4966 , H01L2221/1078
摘要： The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.
摘要翻译： 本发明通过利用原子层沉积（ALD）提供含有IVB族或VB族金属，硅和任选的氮的金属膜。 特别地，本发明提供形成金属硅化物的低温热ALD方法和形成金属氮化硅膜的等离子体增强原子层沉积（PE-ALD）方法。 本发明的方法能够在基材的表面上形成厚度为单层或更薄的金属膜。 本发明中提供的金属膜可用于接触金属化，金属栅极或扩散阻挡层。
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公开(公告)号：US08212218B2
公开(公告)日：2012-07-03
申请号：US12627076
申请日：2009-11-30
申请人： Cyril Cabral, Jr. , Michael S. Gordon , Steven J. Koester , Conal E. Murray , Kenneth P. Rodbell , Stephen M. Rossnagel , Robert L. Wisnieff , Jeng-bang Yau
发明人： Cyril Cabral, Jr. , Michael S. Gordon , Steven J. Koester , Conal E. Murray , Kenneth P. Rodbell , Stephen M. Rossnagel , Robert L. Wisnieff , Jeng-bang Yau
IPC分类号： G01T1/02
CPC分类号： G01T1/026
摘要： A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.
摘要翻译： 用于确定辐射量的系统包括配置成接收辐射量的剂量计，该剂量计包括具有谐振频率的电路，使得电路的谐振频率根据剂量计接收的辐射量而改变， 剂量计还被配置为吸收电路的谐振频率处的RF能量; 射频（RF）发射器，被配置为以共振频率将所述RF能量传输到所述剂量计; 以及接收器，被配置为基于所吸收的RF能量来确定所述剂量计的谐振频率，其中所述辐射量基于所述谐振频率来确定。
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公开(公告)号：US07749898B2
公开(公告)日：2010-07-06
申请号：US12145163
申请日：2008-06-24
申请人： Paul R. Besser , Christian Lavoie , Cyril Cabral, Jr. , Stephen M. Rossnagel , Kenneth P. Rodbell
发明人： Paul R. Besser , Christian Lavoie , Cyril Cabral, Jr. , Stephen M. Rossnagel , Kenneth P. Rodbell
IPC分类号： H01L21/477
CPC分类号： H01L21/76889 , H01L21/76846 , H01L21/76855 , H01L21/76879 , H01L21/76883 , H01L23/485 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region.
摘要翻译： 形成互连结构的方法包括在其中限定有导电区域的第一层之上形成介电层。 在电介质层中限定开口以暴露导电区域的至少一部分。 在开口中形成金属硅化物以限定互连结构。 半导体器件包括其中限定有导电区域的第一层，形成在第一层之上的电介质层和延伸穿过介电层以与导电区域连通的金属硅化物互连结构。
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公开(公告)号：US07023064B2
公开(公告)日：2006-04-04
申请号：US10710063
申请日：2004-06-16
IPC分类号： H01L29/76
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。
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8.发明授权High temperature processing compatible metal gate electrode for pFETS and methods for fabrication 有权用于pFETS的高温处理兼容金属栅电极及其制造方法公开(公告)号：US07863083B2
公开(公告)日：2011-01-04
申请号：US12197845
申请日：2008-08-25
申请人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
发明人： Ricky Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Alessandro C. Callegari , Supratik Guha , Hyungjun Kim , Fenton R. McFeely , Vijay Narayanan , Kenneth P. Rodbell , John J. Yurkas
IPC分类号： H01L21/00 , H01L21/76 , H01L21/266 , H01L21/425
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/3003
摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.
摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。
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公开(公告)号：US07282403B2
公开(公告)日：2007-10-16
申请号：US11203952
申请日：2005-08-15
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。
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10.发明授权Method and structure to reduce soft error rate susceptibility in semiconductor structures 有权减少半导体结构中软错误率敏感性的方法和结构公开(公告)号：US08362600B2
公开(公告)日：2013-01-29
申请号：US12689268
申请日：2010-01-19
申请人： Cyril Cabral, Jr. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
发明人： Cyril Cabral, Jr. , Michael S. Gordon , David F. Heidel , Conal Eugene Murray , Kenneth Parker Rodbell , Henry Hong Ki Tang
IPC分类号： H01L23/556 , H01L21/60
CPC分类号： H01L23/556 , H01L24/13 , H01L2924/01019 , H01L2924/01025 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/1305 , H01L2924/14 , H01L2924/3025 , H01L2924/00
摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.
摘要翻译： 公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个 水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个 位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到 终端垫到达一个设备。
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