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    Analogue to digital conversion device
    2.
    发明授权
    Analogue to digital conversion device 有权
    模拟数字转换设备

    公开(公告)号：US09246507B2

    公开(公告)日：2016-01-26

    申请号：US14669052

    申请日：2015-03-26

    Applicant: DENSO CORPORATION

    Inventor： Tomohito Terazawa

    IPC: H03M1/60 ,  H03M1/14 ,  H03M1/62

    CPC classification number: H03M1/146 ,  H03M1/502 ,  H03M1/60 ,  H03M1/62

    Abstract: An A/D conversion device has an A/D conversion section including A/D conversion units. Each A/D conversion unit has a pulse delay circuit including delay units connected in daisy chain to form a ring delay line. Each delay unit delays a pulse signal by a delay time corresponding to an input voltage. The A/D conversion section counts the number of pulse signals that passed through the delay units during a period counted from a timing when a start signal is switched to an activation level from a non-activation level at a timing when a sampling signal is received. When each two successive timing signals CKi (i=1, 2, . . . and m) have a same specific period. The each two successive timing signals have a different phase shifted by 1/m of the specific period. Each A/D conversion unit receives the timing signal CK1 as the start signal, and the timing signal CKi+1 (CKm+1=CK1) as the sampling signal.

    Abstract translation: A / D转换装置具有包括A / D转换单元的A / D转换部。 每个A / D转换单元具有脉冲延迟电路，包括以菊花链连接的延迟单元以形成环延迟线。 每个延迟单元将脉冲信号延迟与输入电压对应的延迟时间。 A / D转换部分在从接收到采样信号的定时处的非激活电平切换到启动电平的定时期间计数的周期期间，计数通过延迟单元的脉冲信号的数量 。 当每两个连续定时信号CK i（i = 1,2，...和m）具有相同的特定周期时。 每两个连续的定时信号具有不同的相位移位特定周期的1 / m。 每个A / D转换单元接收定时信号CK1作为起始信号，定时信号CKi + 1（CKm + 1 = CK1）作为采样信号。

    Output changing method for an A/D conversion apparatus and A/D conversion apparatus
    4.
    发明授权
    Output changing method for an A/D conversion apparatus and A/D conversion apparatus 有权
    A / D转换装置和A / D转换装置的输出改变方法

    公开(公告)号：US09276600B2

    公开(公告)日：2016-03-01

    申请号：US14635513

    申请日：2015-03-02

    Applicant: DENSO CORPORATION

    Inventor： Tomohito Terazawa

    IPC: H03M1/50 ,  H03M1/12

    CPC classification number: H03M1/12 ,  H03M1/109 ,  H03M1/129 ,  H03M1/502

    Abstract: An output changing method of an A/D conversion apparatus is provided. The apparatus includes a pulse delay circuit in which delay units are connected in series, and an encoding circuit which detects the number of stages of the delay units, through which a pulse signal passes during predetermined measurement time, and generates numeric data corresponding to the number of stages. The apparatus receives an analog input signal as power supply voltage of the pulse delay circuit to perform A/D conversion for the analog input signal. The method includes determining whether or not the analog input signal is within an allowable voltage range in which the apparatus operates normally, outputting the numeric data as an A/D conversion value if the analog input signal is within the range, and outputting numeric data formed of a specified value as the A/D conversion value if the analog input signal is not within the range.

    Abstract translation: 提供了一种A / D转换装置的输出改变方法。 该装置包括延迟单元串联连接的脉冲延迟电路和检测在预定测量时间期间脉冲信号通过的延迟单元的级数的编码电路，并产生与数字对应的数字数据 的阶段。 该装置接收模拟输入信号作为脉冲延迟电路的电源电压，以对模拟输入信号执行A / D转换。 该方法包括：确定模拟输入信号是否在设备正常工作的容许电压范围内，如果模拟输入信号在该范围内，则输出数字数据作为A / D转换值，并输出形成的数字数据 如果模拟输入信号不在该范围内，则为指定值作为A / D转换值。

    Self-resonant circuit
    5.
    发明授权
    Self-resonant circuit 有权
    自谐振电路

    公开(公告)号：US08907731B2

    公开(公告)日：2014-12-09

    申请号：US13740610

    申请日：2013-01-14

    Applicant: Denso Corporation

    Inventor： Shigenori Yamauchi ,  Takamoto Watanabe ,  Tomohito Terazawa

    IPC: H03B5/30 ,  H03L7/00 ,  H03L7/08 ,  G01C19/5776 ,  H03L7/18

    CPC classification number: H03L7/00 ,  G01C19/5776 ,  H03L7/08 ,  H03L7/18 ,  H03L2207/50

    Abstract: A digitally-controlled oscillator circuit receives a digital value and generates a driving signal for driving an oscillator at a frequency according to the received digital value. A time-to-digital converter circuit receives a detection signal of oscillation of the oscillator, receives the driving signal, and detects a phase difference between the detection signal and the driving signal. A control circuit receives the detected phase difference and controls the frequency of the driving signal generated by the digitally-controlled oscillator circuit, such that the detected phase difference coincides with a predetermined resonant phase difference to resonate the oscillator.

    Abstract translation: 数字控制振荡器电路接收数字值，并根据接收到的数字值产生用于以频率驱动振荡器的驱动信号。 时间数字转换器电路接收振荡器的振荡检测信号，接收驱动信号，检测检测信号与驱动信号之间的相位差。 控制电路接收检测到的相位差并控制由数字控制的振荡电路产生的驱动信号的频率，使得检测的相位差与预定的谐振相位差重合，以谐振振荡器。

    Voltage-controlled oscillator and analog-digital converter
    7.
    发明授权
    Voltage-controlled oscillator and analog-digital converter 有权
    压控振荡器和模数转换器

    公开(公告)号：US09577661B2

    公开(公告)日：2017-02-21

    申请号：US15150663

    申请日：2016-05-10

    Applicant: DENSO CORPORATION ,  TOKYO INSTITUTE OF TECHNOLOGY

    Inventor： Akira Matsuzawa ,  Masaya Miyahara ,  Tomohito Terazawa

    IPC: H03M1/60 ,  G05F1/56 ,  H03K3/03 ,  H03F3/45

    CPC classification number: H03M1/60 ,  G05F1/561 ,  H03F3/45 ,  H03F3/45179 ,  H03K3/0315

    Abstract: A voltage-controlled oscillator includes a voltage-current converter, a first ring oscillator and a second ring oscillator. The voltage-current converter includes a first transistor for receiving a first control voltage at its gate terminal, a second transistor for receiving a second control voltage at its gate terminal, a third transistor connected to the first transistor in series and has a gate terminal connected to a drain terminal of the first transistor, a fourth transistor connected to the second transistor in series and has a gate terminal connected to a drain terminal of the second transistor, a resistor connected to a source terminal of the first transistor and a source terminal of the second transistor, a fifth transistor having a gate terminal connected to the drain terminal of the first transistor, and a sixth transistor having a gate terminal connected to the drain terminal of the second transistor.

    Abstract translation: 压控振荡器包括电压 - 电流转换器，第一环形振荡器和第二环形振荡器。 电压 - 电流转换器包括用于在其栅极端接收第一控制电压的第一晶体管，用于在其栅极端接收第二控制电压的第二晶体管，串联连接到第一晶体管的第三晶体管，并且栅极端子连接 到第一晶体管的漏极端子，第四晶体管串联连接到第二晶体管，并且具有连接到第二晶体管的漏极端子的栅极端子，连接到第一晶体管的源极端子的电阻器和连接到第一晶体管的源极端子的源极端子 第二晶体管，具有连接到第一晶体管的漏极端子的栅极端子的第五晶体管，以及具有连接到第二晶体管的漏极端子的栅极端子的第六晶体管。

    Digital controlled oscillator and frequency variable oscillator
    8.
    发明授权
    Digital controlled oscillator and frequency variable oscillator 有权
    数字控制振荡器和变频振荡器

    公开(公告)号：US09160316B2

    公开(公告)日：2015-10-13

    申请号：US14321871

    申请日：2014-07-02

    Applicant: DENSO CORPORATION

    Inventor： Tomohito Terazawa

    IPC: H03K3/03

    CPC classification number: H03K3/0315

    Abstract: A digital controlled oscillator includes: a delay circuit which includes m elements transmitting a pulse signal with delay; a timing signal generator generating a timing signal corresponding to timing-selection data from passing signals, based on the timing-selection data specifying any of timings which are obtained by dividing a circulation period of the pulse signal by m×n; and an output signal generator which sets the timing-selection data based on control data specifying a period of an output pulse signal and the timing-selection data, and generates the output pulse signal based on the timing-selection data by using the timing signal. The timing signal generator generates the timings obtained by dividing the circulation period by m×n by using pulse edge shift circuits which generate n shift signals whose timings differ by a unit delay from one input signal, the unit delay being 1/n of delay time in the element.

    Abstract translation: 数字控制振荡器包括：延迟电路，其包括具有延迟的脉冲信号的m个元件; 定时信号发生器，根据指定通过将脉冲信号的循环周期除以m×n得到的定时的定时选择数据，生成与通过信号对应的定时选择数据的定时信号; 以及输出信号发生器，其基于指定输出脉冲信号的周期的控制数据和定时选择数据来设置定时选择数据，并且通过使用定时信号，基于定时选择数据生成输出脉冲信号。 定时信号发生器通过使用产生与一个输入信号相差一个单位延迟的n个移位信号的脉冲边沿移位电路产生通过将循环周期除以m×n而获得的定时，单位延迟为延迟时间的1 / n 在元素中。

    Analog to digital converter provided with pulse delay circuit
    9.
    发明授权
    Analog to digital converter provided with pulse delay circuit 有权
    具有脉冲延迟电路的模数转换器

    公开(公告)号：US08681028B2

    公开(公告)日：2014-03-25

    申请号：US13622437

    申请日：2012-09-19

    Applicant: DENSO CORPORATION

    Inventor： Tomohito Terazawa

    IPC: H03M1/10

    CPC classification number: H03M1/12 ,  H03M1/0621 ,  H03M1/089 ,  H03M1/1009 ,  H03M1/502

    Abstract: An analog to digital converter includes: a first pulse delay circuit forming a multi-stage delay unit of which each delay unit have a pulse signal delayed with a delay time responding to an input voltage; a first encoding circuit that detects the number of delay units in the first pulse delay circuit through which the pulse signal passes during a predetermined measurement period, and outputs the AD conversion data based on the number of delay units; and a timing generation circuit which, in response to receiving the start signal, generates an end signal when the input voltage of the first pulse delay circuit is a specified voltage within an allowable input voltage range, in order to determine the measurement period which is a time required for the pulse signal to pass through a predetermined number of the delay units which is specified in advance.

    Abstract translation: 模数转换器包括：形成多级延迟单元的第一脉冲延迟电路，其中每个延迟单元具有延迟响应于输入电压的延迟时间的脉冲信号; 第一编码电路，在预定测量周期内检测脉冲信号通过的第一脉冲延迟电路中的延迟单元的数量，并且基于延迟单元的数量输出AD转换数据; 以及定时产生电路，当所述第一脉冲延迟电路的输入电压为可允许的输入电压范围内的指定电压时，响应于接收到所述起始信号而产生结束信号，以便确定所述测量周期为 脉冲信号通过预先指定的预定数量的延迟单元所需的时间。

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