公开(公告)号：US06920080B2

公开(公告)日：2005-07-19

申请号：US10702366

申请日：2003-11-06

申请人： Dae-hyun Chung ,  Sang-woong Shin

发明人： Dae-hyun Chung ,  Sang-woong Shin

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： A synchronous semiconductor memory device includes an output control signal generating circuit that generates a data output control signal in response to an internal clock signal, an output control clock signal and a CAS latency signal. The output control signal generating circuit successively shifts read information signals in response to the internal clock signal and the output control clock signal, both source clocks of which are identical, and generates one of the shifted read information signals as an output control signal for indicating a data output period in response to the CAS latency signal. The synchronous semiconductor memory device can synchronize the source clocks of the clock signals used in the output control signal generating circuit thereby reducing the influence of clock jitter.

摘要翻译： 同步半导体存储器件包括响应于内部时钟信号，输出控制时钟信号和CAS等待时间信号产生数据输出控制信号的输出控制信号产生电路。 输出控制信号发生电路响应于两个源时钟相同的内部时钟信号和输出控制时钟信号连续地移位读信息信号，并产生一个移位读信息信号作为输出控制信号， 数据输出周期响应CAS延迟信号。 同步半导体存储器件可以使输出控制信号发生电路中使用的时钟信号的源时钟同步，从而减少时钟抖动的影响。

公开(公告)号：US06987407B2

公开(公告)日：2006-01-17

申请号：US10744215

申请日：2003-12-22

申请人： Dae-hyun Chung ,  Sang-woong Shin ,  Woo-jin Lee

发明人： Dae-hyun Chung ,  Sang-woong Shin ,  Woo-jin Lee

IPC分类号： H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/222 ,  H03L7/0812

摘要： A delay locked loop (DLL) is provided that includes a phase detector configured to detect a phase error between an internal clock signal and the external clock signal and output a phase error signal. A low pass filter is configured to output a predetermined control signal in response to the phase error signal. A variable delay circuit is configured to change a delay time in response to the predetermined control signal, delay the phase of the external clock signal with respect to the changed delay time, lock the delayed external clock signal and output the internal clock signal. A compensation delay circuit is configured to receive a control voltage based on a delay time introduced by a data output circuit and delay a phase of the internal clock signal for a first delay time based on the control voltage and output the delayed internal clock signal to the phase detector. Methods of compensating a delay for a DLL are also provided.

摘要翻译： 提供了延迟锁定环（DLL），其包括被配置为检测内部时钟信号和外部时钟信号之间的相位误差并输出相位误差信号的相位检测器。 低通滤波器被配置为响应于相位误差信号输出预定的控制信号。 可变延迟电路被配置为响应于预定控制信号改变延迟时间，相对于改变的延迟时间延迟外部时钟信号的相位，锁定延迟的外部时钟信号并输出​​内部时钟信号。 补偿延迟电路被配置为基于由数据输出电路引入的延迟时间接收控制电压，并且基于控制电压延迟内部时钟信号的第一延迟时间的相位，并将延迟的内部时钟信号输出到 相位检测器。 还提供了补偿DLL的延迟的方法。

公开(公告)号：US07577057B2

公开(公告)日：2009-08-18

申请号：US11607970

申请日：2006-12-04

申请人： Soon-seob Lee ,  Sang-woong Shin

发明人： Soon-seob Lee ,  Sang-woong Shin

IPC分类号： G11C8/00

CPC分类号： G11C7/1006

摘要： A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

摘要翻译： 用于在同步半导体存储器件中产生写数据掩码信号的电路包括输出单元和复位控制单元。 输出单元控制同步半导体存储器件的写入数据掩模操作，锁存写入数据屏蔽信号，并响应于内部时钟信号输出内部写入数据屏蔽信号。 响应于表示在执行包括写入数据掩码操作的写入操作时产生的列选择线信号的激活结束点的写入列禁止信号，复位控制单元产生用于复位内部写入数据屏蔽信号的复位信号。 同步半导体存储器件执行包括在无间隙写入操作中的无间隙写入数据掩模操作时，复位信号被去激活，使得写入数据掩蔽信号不被复位。

公开(公告)号：US06708261B1

公开(公告)日：2004-03-16

申请号：US09377428

申请日：1999-08-19

申请人： Sang-woong Shin ,  Gyu-hong Kim

发明人： Sang-woong Shin ,  Gyu-hong Kim

IPC分类号： G06F1206

CPC分类号： H03K5/135 ,  H03K19/01855

摘要： Integrated circuit devices having signal buffers therein include first and second storage devices that are electrically coupled in series and configured so that data can be loaded into the first storage device in-sync with a first clock signal (e.g., external clock signal) and then passed and loaded into the second storage device in-sync with a second clock signal (e.g., internal clock signal). The second clock signal is derived from the first clock signal and may be a delayed version of the first clock signal having an equivalent duty cycle. The buffer also comprises an integrated circuit that operates synchronously with the second clock signal and a transfer device that passes an output of the second storage device to the integrated circuit in-sync with the second clock signal. In this manner, data can be loaded into the integrated circuit in-sync with the same clock signal used to control the integrated circuit even though the data is originally transferred in-sync with another clock signal.

摘要翻译： 其中具有信号缓冲器的集成电路装置包括串联电耦合并被配置为使得可以将数据与第一时钟信号（例如，外部时钟信号）同步地加载到第一存储装置中并随后通过的第一和第二存储装置 并且与第二时钟信号（例如，内部时钟信号）同步地加载到第二存储设备中。 第二时钟信号从第一时钟信号导出，并且可以是具有等效占空比的第一时钟信号的延迟版本。 缓冲器还包括与第二时钟信号同步操作的集成电路和将第二存储装置的输出与第二时钟信号同步地传递到集成电路的传送装置。 以这种方式，数据可以与用于控制集成电路的相同时钟信号同步加载到集成电路中，即使数据最初与另一个时钟信号同步传输。

公开(公告)号：US20070159913A1

公开(公告)日：2007-07-12

申请号：US11607970

申请日：2006-12-04

申请人： Soon-seob Lee ,  Sang-woong Shin

发明人： Soon-seob Lee ,  Sang-woong Shin

IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1006

摘要： A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

摘要翻译： 用于在同步半导体存储器件中产生写数据掩码信号的电路包括输出单元和复位控制单元。 输出单元控制同步半导体存储器件的写入数据掩模操作，锁存写入数据屏蔽信号，并响应于内部时钟信号输出内部写入数据屏蔽信号。 响应于表示在执行包括写入数据掩码操作的写入操作时产生的列选择线信号的激活结束点的写入列禁止信号，复位控制单元产生用于复位内部写入数据屏蔽信号的复位信号。 同步半导体存储器件执行包括在无间隙写入操作中的无间隙写入数据掩模操作时，复位信号被去激活，使得写入数据掩蔽信号不被复位。

公开(公告)号：US06862250B2

公开(公告)日：2005-03-01

申请号：US10877986

申请日：2004-06-29

申请人： Sang-woong Shin

发明人： Sang-woong Shin

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4093 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1072

摘要： An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

摘要翻译： 同步半导体存储器件中的输出控制信号产生电路优选地包括：1）多个可选择的时钟信号传输电路，用于选择性地延迟施加的时钟信号，以响应于预定的CAS等待时间信号产生输出控制时钟信号，其中 多个可选择的时钟信号传送电路中的每一个将一个或多个时间延迟插入到输出控制时钟信号中; 2）采样电路，用于从读取的主信号产生多个输出信号，以及3）选择电路，用于选择 多个输出信号中的一个，从而指示有效的数据输出时间间隔。 一种用于操作输出控制信号产生电路的方法使得时钟信号被延迟可选数量的附加时钟周期，从而仅在数据有效时确保数据信号的输出。

公开(公告)号：US06396310B2

公开(公告)日：2002-05-28

申请号：US09903128

申请日：2001-07-11

申请人： Sang-woong Shin

发明人： Sang-woong Shin

IPC分类号： G11C706

CPC分类号： G11C7/062 ,  G11C2207/063

摘要： Integrated circuit memory devices according to the present invention include a current sense amplifier having first and second cross-coupled sensing transistors. First and second data lines are electrically coupled to the source of the first sensing transistor and the source of the second sensing transistor, respectively. The current sense amplifier includes a first load transistor that has a source electrically connected to a drain of the first sensing transistor and a gate of the second sensing transistor and a second load transistor is included that has a source electrically connected to a drain of the second sensing transistor and a gate of the first sensing transistor. A switching transistor is responsive to an enable signal and has a source electrically coupled to a drain of the first load transistor and a drain of said second load transistor. A first load circuit provides a variable impedance across the source and the drain of the first load transistor in response to at least a first sense signal.

公开(公告)号：US08310859B2

公开(公告)日：2012-11-13

申请号：US12570159

申请日：2009-09-30

申请人： Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

发明人： Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

IPC分类号： G11C11/24

CPC分类号： G11C8/14 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

摘要： A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

摘要翻译： 半导体存储器件包括多个存储单元块，它们包括具有位线的第一存储单元块，边沿读出放大器块，其包括耦合到第一存储单元块的位线的一部分的边沿读出放大器，以及平衡电容器单元 耦合到边缘读出放大器。

公开(公告)号：US06778465B2

公开(公告)日：2004-08-17

申请号：US10290285

申请日：2002-11-08

申请人： Sang-woong Shin

发明人： Sang-woong Shin

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1072

摘要： An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

摘要翻译： 同步半导体存储器件中的输出控制信号产生电路优选地包括：1）多个可选择的时钟信号传输电路，用于选择性地延迟施加的时钟信号，以响应于预定的CAS等待时间信号产生输出控制时钟信号，其中 多个可选择的时钟信号传送电路中的每一个将一个或多个时间延迟插入到输出控制时钟信号中; 2）采样电路，用于从读取的主信号产生多个输出信号，以及3）选择电路，用于选择 多个输出信号中的一个，从而指示有效的数据输出时间间隔。 一种用于操作输出控制信号产生电路的方法使得时钟信号被延迟可选数量的附加时钟周期，从而仅在数据有效时确保数据信号的输出。