公开(公告)号：US08310859B2

公开(公告)日：2012-11-13

申请号：US12570159

申请日：2009-09-30

申请人： Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

发明人： Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

IPC分类号： G11C11/24

CPC分类号： G11C8/14 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

摘要： A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

摘要翻译： 半导体存储器件包括多个存储单元块，它们包括具有位线的第一存储单元块，边沿读出放大器块，其包括耦合到第一存储单元块的位线的一部分的边沿读出放大器，以及平衡电容器单元 耦合到边缘读出放大器。

公开(公告)号：US08283714B2

公开(公告)日：2012-10-09

申请号：US13085898

申请日：2011-04-13

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

公开(公告)号：US20080211013A1

公开(公告)日：2008-09-04

申请号：US12118268

申请日：2008-05-09

申请人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/7827

摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

摘要翻译： 在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个 支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。 形成围绕每个支柱部分的栅电极。 位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。 字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。 第一掺杂区域形成在柱的每个柱部分的上表面中。 第二掺杂区形成在柱的主体部分上并与电位线连接。 存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

公开(公告)号：US20110186923A1

公开(公告)日：2011-08-04

申请号：US13085898

申请日：2011-04-13

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/78

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

公开(公告)号：US20100285654A1

公开(公告)日：2010-11-11

申请号：US12839573

申请日：2010-07-20

申请人： Hyeoung-won Seo

发明人： Hyeoung-won Seo

IPC分类号： H01L21/762

CPC分类号： H01L23/562 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.

摘要翻译： 半导体器件及其制造方法减少了模头翘曲。 半导体器件包括基片和基本上在基片的整个表面上延伸的第一材料层。 应力消除模式存在于并穿过第一层，以便将第一层划分成至少两个离散部分。 应力消除图案可以是第一层的离散部分之间的界面的形式，或者与第一层的材料不同的材料壁。

公开(公告)号：US20080179647A1

公开(公告)日：2008-07-31

申请号：US11964146

申请日：2007-12-26

申请人： Hyeoung-won Seo ,  Dong-hyun Kim ,  Kang-yoon Lee ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Dong-hyun Kim ,  Kang-yoon Lee ,  Seong-goo Kim

IPC分类号： H01L27/108 ,  H01L21/8239

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876

摘要： A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.

摘要翻译： 公开了一种包括阻挡绝缘层和相关制造方法的半导体器件。 半导体器件半导体衬底包括多个有源区，其中有源区由器件隔离层限定，并沿着第一方向设置; 连接到有源区的多个位线电极，其中每个位线电极沿着第二方向延伸; 以及多个第一阻挡绝缘层。 每个第一阻挡绝缘层沿着第三方向延伸，至少一个第一阻挡绝缘层设置在设置在两个有源区之间的器件隔离层的对应的第一部分上，两个有源区相邻 沿第一方向，第一方向和第二方向彼此不同。

公开(公告)号：US07387931B2

公开(公告)日：2008-06-17

申请号：US11546581

申请日：2006-10-11

申请人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

发明人： Hyeoung-won Seo ,  Jae-man Yoon ,  Kang-yoon Lee ,  Dong-gun Park ,  Bong-soo Kim ,  Seong-goo Kim

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/7827

摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

摘要翻译： 在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个 支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。 形成围绕每个支柱部分的栅电极。 位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。 字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。 第一掺杂区域形成在柱的每个柱部分的上表面中。 第二掺杂区形成在柱的主体部分上并与电位线连接。 存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

公开(公告)号：US07279775B2

公开(公告)日：2007-10-09

申请号：US11235320

申请日：2005-09-27

申请人： Sun-joon Kim ,  Hyeoung-won Seo

发明人： Sun-joon Kim ,  Hyeoung-won Seo

IPC分类号： H01L23/544

CPC分类号： H01L23/3178 ,  H01L23/3192 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.

摘要翻译： 公开了一种半导体管芯及相关的半导体晶片处理方法，其中具有不同构型的凹陷区域并限定划线的第一层间绝缘体与形成有特征倾斜侧表面的至少一个保护层相关联。

公开(公告)号：US08871614B2

公开(公告)日：2014-10-28

申请号：US12961795

申请日：2010-12-07

申请人： Sun-joon Kim ,  Hyeoung-won Seo

发明人： Sun-joon Kim ,  Hyeoung-won Seo

IPC分类号： H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3178 ,  H01L23/3192 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.

摘要翻译： 公开了一种半导体管芯及相关的半导体晶片处理方法，其中具有不同构型的凹陷区域并限定划线的第一层间绝缘体与形成有特征倾斜侧表面的至少一个保护层相关联。

公开(公告)号：US20120273898A1

公开(公告)日：2012-11-01

申请号：US13549648

申请日：2012-07-16

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件