-
1.发明申请Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same 有权用于板级接头的低温焊料的应力消除层和应力补偿套圈及其制造方法公开(公告)号：US20060068579A1
公开(公告)日：2006-03-30
申请号：US10954999
申请日：2004-09-29
申请人： Daewoong Suh , Saikumar Jayaraman , Stephen Lehman , Mitesh Patel , Tiffany Byrne , Edward Martin , Mohd Erwan Basiron , Wei Keat Loh , Sheau Hooi Lim , Yoong Tatt Chin
发明人： Daewoong Suh , Saikumar Jayaraman , Stephen Lehman , Mitesh Patel , Tiffany Byrne , Edward Martin , Mohd Erwan Basiron , Wei Keat Loh , Sheau Hooi Lim , Yoong Tatt Chin
IPC分类号： H01L21/44
CPC分类号： H05K3/3436 , H01L23/562 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/00014 , H01L2924/01012 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H05K1/0271 , H05K3/3463 , H05K2201/10977 , H05K2203/0126 , Y02P70/613 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
摘要翻译： 通过在基底下表面上分配聚合物以部分地嵌入设置在下表面上的低熔点焊料凸点的条件来形成应力消除层。 应力消除层流向低熔点焊料凸块。 应力补偿轴环形成在与基板相配合的基板上，并且应力补偿套环部分嵌入低熔点焊料凸块。 还包括展示应力消除层和应力补偿套环的物品。 还包括包括低熔点焊料，应力消除层和应力补偿环的计算系统。
-
2.发明申请STRESS-RELIEF LAYERS AND STRESS-COMPENSATION COLLARS WITH LOW-TEMPERATURE SOLDERS FOR BOARD-LEVEL JOINTS, AND PROCESSES OF MAKING SAME 有权用于板级接头的低温焊料的应力缓和层和应力补偿胶料及其制造方法公开(公告)号：US20070190772A1
公开(公告)日：2007-08-16
申请号：US11736280
申请日：2007-04-17
申请人： Daewoong Suh , Saikumar Jayaraman , Stephen Lehman , Mitesh Patel , Tiffany Byrne , Eward Martin , Mohd Erwan Basiron , Wei Loh , Sheau Lim , Yoong Tatt Chin
发明人： Daewoong Suh , Saikumar Jayaraman , Stephen Lehman , Mitesh Patel , Tiffany Byrne , Eward Martin , Mohd Erwan Basiron , Wei Loh , Sheau Lim , Yoong Tatt Chin
IPC分类号： H01L21/44
CPC分类号： H05K3/3436 , H01L23/562 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/00014 , H01L2924/01012 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H05K1/0271 , H05K3/3463 , H05K2201/10977 , H05K2203/0126 , Y02P70/613 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
摘要翻译： 通过在基底下表面上分配聚合物以部分地嵌入设置在下表面上的低熔点焊料凸点的条件来形成应力消除层。 应力消除层流向低熔点焊料凸块。 应力补偿轴环形成在与基板相配合的基板上，并且应力补偿套环部分嵌入低熔点焊料凸块。 还包括展示应力消除层和应力补偿套环的物品。 还包括包括低熔点焊料，应力消除层和应力补偿环的计算系统。
-
公开(公告)号：US07253088B2
公开(公告)日：2007-08-07
申请号：US10954999
申请日：2004-09-29
申请人： Daewoong Suh , Saikumar Jayaraman , Stephen E. Lehman , Mitesh Patel , Tiffany A. Byrne , Edward L. Martin , Mohd Erwan B. Basiron , Wei Keat Loh , Sheau Hooi Lim , Yoong Tatt P. Chin
发明人： Daewoong Suh , Saikumar Jayaraman , Stephen E. Lehman , Mitesh Patel , Tiffany A. Byrne , Edward L. Martin , Mohd Erwan B. Basiron , Wei Keat Loh , Sheau Hooi Lim , Yoong Tatt P. Chin
IPC分类号： H01L21/44
CPC分类号： H05K3/3436 , H01L23/562 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/00014 , H01L2924/01012 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H05K1/0271 , H05K3/3463 , H05K2201/10977 , H05K2203/0126 , Y02P70/613 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
-
4.发明授权Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same 有权用于板级接头的低温焊料的应力消除层和应力补偿套圈及其制造方法公开(公告)号：US07291548B2
公开(公告)日：2007-11-06
申请号：US11736280
申请日：2007-04-17
申请人： Daewoong Suh , Saikumar Jayaraman , Stephen E. Lehman , Mitesh Patel , Tiffany A. Byrne , Edward L. Martin , Mohd Erwan B. Basiron , Wei Keat Loh , Sheau Hooi Lim , Yoong Tatt P. Chin
发明人： Daewoong Suh , Saikumar Jayaraman , Stephen E. Lehman , Mitesh Patel , Tiffany A. Byrne , Edward L. Martin , Mohd Erwan B. Basiron , Wei Keat Loh , Sheau Hooi Lim , Yoong Tatt P. Chin
IPC分类号： H01L21/44
CPC分类号： H05K3/3436 , H01L23/562 , H01L24/16 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/00014 , H01L2924/01012 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H05K1/0271 , H05K3/3463 , H05K2201/10977 , H05K2203/0126 , Y02P70/613 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
摘要翻译： 通过在基底下表面上分配聚合物以部分地嵌入设置在下表面上的低熔点焊料凸点的条件来形成应力消除层。 应力消除层流向低熔点焊料凸块。 应力补偿轴环形成在与基板相配合的基板上，并且应力补偿套环部分嵌入低熔点焊料凸块。 还包括展示应力消除层和应力补偿套环的物品。 还包括包括低熔点焊料，应力消除层和应力补偿环的计算系统。
-
5.发明授权Stress-relief layer and stress-compensation collar in contact arrays, and processes of making same 有权接触阵列中的应力消除层和应力补偿环，以及制造相同的工艺公开(公告)号：US07244634B2
公开(公告)日：2007-07-17
申请号：US10815968
申请日：2004-03-31
申请人： Daewoong Suh , Saikumar Jayaraman , Mohd Erwan P. Bin Basiron , Sheau Hooi Lim , Yoong Tatt P. Chin
发明人： Daewoong Suh , Saikumar Jayaraman , Mohd Erwan P. Bin Basiron , Sheau Hooi Lim , Yoong Tatt P. Chin
IPC分类号： H01L21/00
CPC分类号： H05K3/3436 , H01L23/49816 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01077 , H01L2924/15311 , H05K1/0271 , H05K2201/10977 , H05K2203/0126 , H05K2203/1189 , Y02P70/613 , H01L2224/05599
摘要： A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. A stress-compensation collar is formed on a board to which the substrate is mated and the SCC partially embeds the solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes a stress-relief layer and a stress-compensation collar is also included.
摘要翻译： 通过在基底下表面上分配聚合物以部分地嵌入设置在下表面上的焊料凸块的条件来形成应力消除层。 应力消除层流向焊料凸块。 应力补偿轴环形成在与基板配合的板上，并且SCC部分地嵌入焊料凸块。 还包括展示应力消除层和应力补偿套环的物品。 还包括一个包括应力消除层和应力补偿环的计算系统。
-
6.发明授权Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same 有权具有用于体偏置的电介质障碍物的芯片封装热界面材料，其使用方法以及含有它们的体系公开(公告)号：US07332807B2
公开(公告)日：2008-02-19
申请号：US11323512
申请日：2005-12-30
CPC分类号： H01L23/3737 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/2929 , H01L2224/293 , H01L2224/29486 , H01L2224/2949 , H01L2224/29499 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/01327 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/05599
摘要： A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
摘要翻译： 芯片封装包括设置在模具背面和散热器之间的热界面材料。 热界面材料包括由电介质膜覆盖的第一金属颗粒。 电介质膜选自第一金属的无机化合物或第二金属的无机化合物涂层。 电介质膜减少热界面材料中的第一金属颗粒的总传热量，而不需要电介质膜的总可能传热的一小部分。 一种操作该芯片的方法包括：将该电介质膜的芯片偏压就位。
-
7.发明申请CHIP PACKAGE THERMAL INTERFACE MATERIALS WITH DIELECTRIC OBSTRUCTIONS FOR BODY-BIASING, METHODS OF USING SAME, AND SYSTEMS CONTAINING SAME 有权芯片封装具有用于机身偏转的电介质阻抗的热接口材料，使用它们的方法以及包含其的系统公开(公告)号：US20080064144A1
公开(公告)日：2008-03-13
申请号：US11935597
申请日：2007-11-06
申请人： Ashay Dani , Saikumar Jayaraman , Mitesh Patel , Vijay Wakharkar
发明人： Ashay Dani , Saikumar Jayaraman , Mitesh Patel , Vijay Wakharkar
CPC分类号： H01L23/3737 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/2929 , H01L2224/293 , H01L2224/29486 , H01L2224/2949 , H01L2224/29499 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/01327 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/05599
摘要： A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
摘要翻译： 芯片封装包括设置在模具背面和散热器之间的热界面材料。 热界面材料包括由电介质膜覆盖的第一金属颗粒。 电介质膜选自第一金属的无机化合物或第二金属的无机化合物涂层。 电介质膜减少热界面材料中的第一金属颗粒的总传热量，而不需要电介质膜的总可能传热的一小部分。 一种操作该芯片的方法包括：将该电介质膜的芯片偏压就位。
-
8.发明申请Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same 有权具有用于体偏置的电介质障碍物的芯片封装热界面材料，其使用方法以及含有它们的体系公开(公告)号：US20070158823A1
公开(公告)日：2007-07-12
申请号：US11323512
申请日：2005-12-30
申请人： Ashay Dani , Anna Prakash , Saikumar Jayaraman , Mitesh Patel , Vijay Wakharkar
发明人： Ashay Dani , Anna Prakash , Saikumar Jayaraman , Mitesh Patel , Vijay Wakharkar
IPC分类号： H01L23/34
CPC分类号： H01L23/3737 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/2929 , H01L2224/293 , H01L2224/29486 , H01L2224/2949 , H01L2224/29499 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/01327 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/05599
摘要： A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
摘要翻译： 芯片封装包括设置在模具背面和散热器之间的热界面材料。 热界面材料包括由电介质膜覆盖的第一金属颗粒。 电介质膜选自第一金属的无机化合物或第二金属的无机化合物涂层。 电介质膜减少热界面材料中的第一金属颗粒的总传热量，而不需要电介质膜的总可能传热的一小部分。 一种操作该芯片的方法包括：将该电介质膜的芯片偏压就位。
-
公开(公告)号：US09929080B2
公开(公告)日：2018-03-27
申请号：US10990228
申请日：2004-11-15
申请人： Daewoong Suh , Saikumar Jayaraman
发明人： Daewoong Suh , Saikumar Jayaraman
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/563 , H01L23/562 , H01L2924/0002 , H01L2924/15311 , H05K3/305 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/043 , H05K2203/0568 , Y02P70/613 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.
-
10.发明授权Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same 有权具有用于体偏置的电介质障碍物的芯片封装热界面材料，其使用方法以及含有它们的体系公开(公告)号：US07776657B2
公开(公告)日：2010-08-17
申请号：US11935597
申请日：2007-11-06
IPC分类号： H01L21/00
CPC分类号： H01L23/3737 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/2929 , H01L2224/293 , H01L2224/29486 , H01L2224/2949 , H01L2224/29499 , H01L2224/32245 , H01L2224/73253 , H01L2924/00014 , H01L2924/01079 , H01L2924/01327 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/05599
摘要： A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
摘要翻译： 芯片封装包括设置在模具背面和散热器之间的热界面材料。 热界面材料包括由电介质膜覆盖的第一金属颗粒。 电介质膜选自第一金属的无机化合物或第二金属的无机化合物涂层。 电介质膜减少热界面材料中的第一金属颗粒的总传热量，而不需要电介质膜的总可能传热的一小部分。 一种操作该芯片的方法包括：将该电介质膜的芯片偏压就位。
-
-
-
-
-
-
-
-
-
搜索结果
98 条记录 (耗时 0.048 秒)
