公开(公告)号：US20160358884A1

公开(公告)日：2016-12-08

申请号：US14731209

申请日：2015-06-04

申请人： Daniel Cavasin ,  Kaushik Mysore Srinivasa Setty

发明人： Daniel Cavasin ,  Kaushik Mysore Srinivasa Setty

IPC分类号： H01L23/00 ,  B23K35/02 ,  H01L23/498 ,  B23K1/00 ,  H01L23/053 ,  H01L23/367

CPC分类号： H01L24/83 ,  B23K1/0016 ,  B23K35/0233 ,  B23K35/0244 ,  B23K2101/40 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4827 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/03828 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/27334 ,  H01L2224/27442 ,  H01L2224/27849 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29211 ,  H01L2224/29295 ,  H01L2224/293 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83487 ,  H01L2224/83493 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/94 ,  H01L2924/16152 ,  H01L2924/165 ,  H01L2924/1659 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2924/01014 ,  H01L2924/01006 ,  H01L2924/05032 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2924/0105 ,  H01L2924/01327

摘要： Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.

摘要翻译： 公开了各种装置和方法。 一方面，提供了在半导体芯片上制造热界面材料的方法。 该方法包括将第一金属和第二金属的组合的预成型件放置在半导体芯片或盖子之一上。 预成型坯是液相烧结的，以使组合演变成平衡组成并结合到半导体芯片。

公开(公告)号：US09780067B2

公开(公告)日：2017-10-03

申请号：US14731209

申请日：2015-06-04

申请人： Daniel Cavasin ,  Kaushik Mysore Srinivasa Setty

发明人： Daniel Cavasin ,  Kaushik Mysore Srinivasa Setty

IPC分类号： H01L23/12 ,  H01L23/00 ,  B23K1/00 ,  B23K35/02 ,  H01L23/373 ,  H01L23/367

CPC分类号： H01L24/83 ,  B23K1/0016 ,  B23K35/0233 ,  B23K35/0244 ,  B23K2101/40 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4827 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/03828 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/27334 ,  H01L2224/27442 ,  H01L2224/27849 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29211 ,  H01L2224/29295 ,  H01L2224/293 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32507 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/83469 ,  H01L2224/83487 ,  H01L2224/83493 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/94 ,  H01L2924/16152 ,  H01L2924/165 ,  H01L2924/1659 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2924/01014 ,  H01L2924/01006 ,  H01L2924/05032 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2924/0105 ,  H01L2924/01327

摘要： Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.

公开(公告)号：US10312221B1

公开(公告)日：2019-06-04

申请号：US15844575

申请日：2017-12-17

申请人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

发明人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC分类号： H01L23/52 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.

公开(公告)号：US20190189590A1

公开(公告)日：2019-06-20

申请号：US15844575

申请日：2017-12-17

申请人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

发明人： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.