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1.发明授权公开(公告)号：US07371311B2
公开(公告)日：2008-05-13
申请号：US10682276
申请日：2003-10-08
CPC分类号： C25D21/12
摘要： An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.
摘要翻译： 本发明的一个实施方案提供了一种通过改变低酸性电镀溶液的组分浓度来减小模内厚度变化的方法。 对于一个实施例，调平器浓度被充分增加以将模具厚度变化减小到指定值。 对于本发明的一个实施例，矫直机和抑制器增加以减小模内厚度变化并且基本上减少多个电镀缺陷。 在这样的实施例中，确定矫直机和抑制器的组合浓度以保持足够的间隙填充。
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2.发明申请Methods for reducing protrusions and within die thickness variations on plated thin film 审中-公开减少电镀薄膜上突起和模内厚度变化的方法公开(公告)号：US20060091018A1
公开(公告)日：2006-05-04
申请号：US11292609
申请日：2005-12-01
申请人： Yang Cao , Vinay Chikarmane , Rajiv Rastogi , Daniel Zierath
发明人： Yang Cao , Vinay Chikarmane , Rajiv Rastogi , Daniel Zierath
CPC分类号： H01L21/2885 , C25D5/18
摘要： Embodiments of the invention provide methods for electroplating a substrate that substantially reduce or eliminate protrusions and decrease WID thickness variations. The number of protrusions formed on the plating surface is highly dependent upon the electroplating current density. Embodiments of the invention vary the electroplating current waveform by implementing an initial current step sufficient to fill substrate features and a terminal current step sufficient to achieve the specified plating thickness while suppressing protrusions and within die thickness variations.
摘要翻译： 本发明的实施例提供了用于电镀基板的方法，其基本上减少或消除突起并减小WID厚度变化。 形成在电镀表面上的突起的数量高度取决于电镀电流密度。 本发明的实施例通过实施足以填充基板特征的初始电流步骤和足以在抑制突起和模具厚度变化的同时实现特定电镀厚度的端电流步骤来改变电镀电流波形。
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公开(公告)号：US20050285269A1
公开(公告)日：2005-12-29
申请号：US10881778
申请日：2004-06-29
申请人： Yang Cao , Robert Wu , Yue Ma , Chia-Hong Jan , Vinay Chikarmane , Rajiv Rastogi
发明人： Yang Cao , Robert Wu , Yue Ma , Chia-Hong Jan , Vinay Chikarmane , Rajiv Rastogi
IPC分类号： H01L21/425 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： A die is provided with an insulation layer and an interconnect. The interconnect has been recrystallized to reduce void content.
摘要翻译： 模具设置有绝缘层和互连。 互连已经重结晶以减少空隙含量。
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公开(公告)号：US20050112856A1
公开(公告)日：2005-05-26
申请号：US10981207
申请日：2004-11-03
IPC分类号： B32B9/00 , C25D5/34 , H01L21/02 , H01L21/20 , H01L21/288 , H01L21/768
CPC分类号： H01L21/02068 , C25D5/34 , H01L21/2885 , H01L21/76843 , H01L21/76861 , H01L21/76864 , H01L21/76873 , Y10T428/24926
摘要： Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
摘要翻译： 种子层处理以除去种子层中可能导致在互连电路特征中形成空隙的杂质。 在一个实施方案中，种子层在还原环境中被加热。 在另一个实施方案中，种子层用表面活性剂洗涤，该表面活性剂与在种子层上形成电路特征的其余部分时所用的表面活性剂相容。 又一实施例结合了两种技术。
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公开(公告)号：US20080026556A1
公开(公告)日：2008-01-31
申请号：US11496291
申请日：2006-07-31
IPC分类号： H01L21/44
CPC分类号： H01L21/76844 , H01L21/76831
摘要： A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration can be improved while, at the same time, interconnect and contact resistances can be kept low and array leakage can be mitigated.
摘要翻译： 提供了一种屏障结构，其包括被选择用于与铜接触应用相结合的不同材料。 一些阻挡材料形成在沟槽接触侧壁上，并且在沟槽接触底部上形成其它不同的阻挡材料。 通过选择适当的阻挡材料，可以改善电迁移，同时可以将互连和接触电阻保持在较低水平，并可以减轻阵列泄漏。
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6.发明申请Method for improving electroplating in sub-0.1um interconnects by adjusting immersion conditions 审中-公开通过调整浸入条件来改善0.1μm以下互连电镀的方法公开(公告)号：US20060006071A1
公开(公告)日：2006-01-12
申请号：US11225493
申请日：2005-09-12
申请人： Guangli Che , Vinay Chikarmane , Christopher Thomas , Robert Wu , Daniel Zierath
发明人： Guangli Che , Vinay Chikarmane , Christopher Thomas , Robert Wu , Daniel Zierath
CPC分类号： C25D7/123 , C25D5/18 , C25D17/001
摘要： Embodiments of the invention provide methods of reducing electroplating defects by adjusting immersion conditions. For one embodiment, the immersion conditions are adjusted based upon characteristics of the substrate, including feature size. Additionally or alternatively, the immersion conditions may be adjusted based upon aspects of the electroplating process, including motion of the substrate upon immersion. Immersion conditions that may be adjusted in accordance with various embodiments of the invention include entry bias voltage/current, vertical immersion speed, and angle of immersion.
摘要翻译： 本发明的实施例提供了通过调节浸渍条件来减少电镀缺陷的方法。 对于一个实施例，基于衬底的特性（包括特征尺寸）来调整浸渍条件。 另外或替代地，浸渍条件可以基于电镀工艺的方面来进行调整，包括浸渍时基片的运动。 根据本发明的各种实施例可以调节的浸渍条件包括入口偏置电压/电流，垂直浸入速度和浸入角度。
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公开(公告)号：US20050274619A1
公开(公告)日：2005-12-15
申请号：US11207305
申请日：2005-08-19
申请人： Daniel Zierath , Vinay Chikarmane , Valery Dubin
发明人： Daniel Zierath , Vinay Chikarmane , Valery Dubin
CPC分类号： C25D21/12
摘要： An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.
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公开(公告)号：US07525197B2
公开(公告)日：2009-04-28
申请号：US11496291
申请日：2006-07-31
IPC分类号： H01L21/44
CPC分类号： H01L21/76844 , H01L21/76831
摘要： A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration can be improved while, at the same time, interconnect and contact resistances can be kept low and array leakage can be mitigated.
摘要翻译： 提供了一种屏障结构，其包括被选择用于与铜接触应用相结合的不同材料。 一些阻挡材料形成在沟槽接触侧壁上，并且在沟槽接触底部上形成其它不同的阻挡材料。 通过选择适当的阻挡材料，可以改善电迁移，同时可以将互连和接触电阻保持在较低水平，并可以减轻阵列泄漏。
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公开(公告)号：US20080079165A1
公开(公告)日：2008-04-03
申请号：US11540199
申请日：2006-09-29
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of barriers to use in semiconductor devices are presented herein.
摘要翻译： 这里给出了在半导体器件中使用的屏障的实施例。
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公开(公告)号：US20090170309A1
公开(公告)日：2009-07-02
申请号：US12380377
申请日：2009-02-26
IPC分类号： H01L21/768
CPC分类号： H01L21/76844 , H01L21/76831
摘要： A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration can be improved while, at the same time, interconnect and contact resistances can be kept low and array leakage can be mitigated.
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