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公开(公告)号：US07741928B1
公开(公告)日：2010-06-22
申请号：US12247869
申请日：2008-10-08
申请人： David Cousinard , Philippe Mosch , Lydi Smaini , Randy Tsang , Cao-Thong Tu , Miljan Vuletic
发明人： David Cousinard , Philippe Mosch , Lydi Smaini , Randy Tsang , Cao-Thong Tu , Miljan Vuletic
摘要： Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.
摘要翻译： 使用数字频率锁相环（DFLL）进行频率调制（FM）的电路和方法。 数字控制振荡器（DCO）基于数字调谐字产生和调整调制信号的频率。 DFLL控制逻辑电路接收调制信号的反馈并产生载波信号字。 Σ-Δ调制器电路接收输入信号并施加抖动以产生抖动输入信号字。 加法器电路接收并加法抖动输入信号字和载波信号字以产生数字调谐字。 DFLL控制逻辑电路调整载波信号字以锁定调制信号的载波频率。
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公开(公告)号：US08600324B1
公开(公告)日：2013-12-03
申请号：US12487425
申请日：2009-06-18
申请人： David Cousinard , Cao-Thong Tu , Miljan Vuletic , Lydi Smaini
发明人： David Cousinard , Cao-Thong Tu , Miljan Vuletic , Lydi Smaini
摘要： In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.
摘要翻译： 在一个实施例中，本发明包括以不同频率产生振荡信号的方法。 该方法包括配置数字控制振荡器（DCO）。 DCO被配置为以第一频率产生振荡信号，并且DCO被配置为以第二频率产生振荡信号。 另外，DCO被配置为在转换时段期间从第一频率转换到第二频率。 在转换时段期间，DCO激活第二频率并在多个时间间隔期间停用第一频率。 用于激活第二频率和停用第一频率的时间间隔从转换时间段的开始到转换时间段的结束继续增加。
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公开(公告)号：US08031020B1
公开(公告)日：2011-10-04
申请号：US12433574
申请日：2009-04-30
申请人： Cao-Thong Tu , David Cousinard , Michel Moser
发明人： Cao-Thong Tu , David Cousinard , Michel Moser
CPC分类号： H03L1/00 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03B2200/0088 , H03K3/013 , H03K3/354
摘要： In one embodiment, the present invention includes noise reduction circuits and methods. In one embodiment, cross coupled switching transistors incorporate bias voltages between the control terminal of each transistor and the drain of the other transistor. The bias voltages increase the voltage on each transistors drain terminal and reduce noise upconversion in the system. In one embodiment, the source voltages of each transistor may be increased to linearize the circuit and further reduce noise. In another embodiment, a current is coupled to a PN junction to generate a low noise bias voltage. The bias voltage is used to bias capacitors of a selectively activated and deactivated capacitance to reduce noise. Features and advantages of the present invention may be implemented in an oscillator circuit, which may be used in a communication system, for example.
摘要翻译： 在一个实施例中，本发明包括降噪电路和方法。 在一个实施例中，交叉耦合开关晶体管在每个晶体管的控制端和另一个晶体管的漏极之间并入偏置电压。 偏置电压增加了每个晶体管漏极端子上的电压，并减少了系统中的噪声上变频。 在一个实施例中，可以增加每个晶体管的源电压以使电路线性化并进一步降低噪声。 在另一个实施例中，电流耦合到PN结以产生低噪声偏置电压。 偏置电压用于偏置选择性激活和去激活电容的电容，以减少噪声。 本发明的特征和优点可以在例如可以在通信系统中使用的振荡器电路中实现。
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公开(公告)号：US08442470B1
公开(公告)日：2013-05-14
申请号：US12778236
申请日：2010-05-12
申请人： Cao-Thong Tu , David Cousinard , Frederic Declercq
发明人： Cao-Thong Tu , David Cousinard , Frederic Declercq
IPC分类号： H04B15/00
CPC分类号： H04B1/525
摘要： A system includes a weighting module, a mixer module, and a frequency selective impedance (FSI). The weighting module is configured to receive an input signal having an amplitude and to generate weighted outputs. Amplitudes of the weighted outputs have ratios relative to the amplitude of the input signal. The mixer module has switches configured to receive the weighted outputs and to generate a staircase waveform when the switches are clocked by clock signals. Amplitudes of steps of the staircase waveform are based on the ratios. The FSI is configured to communicate with the switches. The switches are configured to translate an impedance of the FSI centered on a first frequency to a second frequency determined by a frequency of the clock signals.
摘要翻译： 系统包括加权模块，混频器模块和频率选择阻抗（FSI）。 加权模块被配置为接收具有幅度的输入信号并产生加权输出。 加权输出的幅度相对于输入信号的幅度具有比例。 混频器模块具有被配置为接收加权输出并且当开关由时钟信号计时时产生阶梯波形的开关。 阶梯波形的幅度基于比率。 FSI配置为与交换机进行通信。 开关被配置为将以第一频率为中心的FSI的阻抗转换为由时钟信号的频率确定的第二频率。
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公开(公告)号：US07724067B1
公开(公告)日：2010-05-25
申请号：US11729471
申请日：2007-03-29
申请人： Cao-Thong Tu , David Cousinard
发明人： Cao-Thong Tu , David Cousinard
IPC分类号： H03K17/687
CPC分类号： H03K17/687 , H03K2217/0018 , H03K2217/0054
摘要： A body switch system includes a timing module that generates a plurality of clock signals, an input node that receives an input signal, an output node that transmits an output signal; and a body switch circuit that selectively couples a body of a first transistor of a plurality of transistors to one of the input node and the output node and a body of a second transistor of the plurality of transistors to the other one of the input node and the output node based on the plurality of clock signals.
摘要翻译： 身体切换系统包括产生多个时钟信号的定时模块，接收输入信号的输入节点，发送输出信号的输出节点; 以及主体开关电路，其将多个晶体管的第一晶体管的主体选择性地耦合到所述输入节点和所述输出节点之一以及所述多个晶体管的第二晶体管的主体到所述输入节点和 所述输出节点基于所述多个时钟信号。
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公开(公告)号：US08428535B1
公开(公告)日：2013-04-23
申请号：US12175034
申请日：2008-07-17
申请人： David Cousinard , Patrick Clement , Cao-Thong Tu
发明人： David Cousinard , Patrick Clement , Cao-Thong Tu
摘要： A controller in a receiver monitors RSSI and AGC gain levels to determine signal conditions and adjust filter performance accordingly to optimize power consumption while providing acceptable signal quality. When RSSI level is high and AGC gain is low, a strong signal-of-interest is present. In this case, adaptive filter bias currents may be reduced raise the noise floor and degrade intermodulation to reduce power consumption because the strong signal-of-interest can tolerate the higher noise and distortion. When the RSSI level is low and AGC gain is high, a weak signal is present a low noise mode may be effected by increasing bias current to filters used to lower the noise floor, but intermodulation effects may still be tolerated so those filters may be cut back. Other cases are supported. RSSI and AGC gain level thresholds may be dynamically altered based on relative RSSI and AGC levels.
摘要翻译： 接收机中的控制器监视RSSI和AGC增益电平，以确定信号状况并相应地调整滤波器性能，以优化功耗，同时提供可接受的信号质量。 当RSSI电平高且AGC增益低时，存在强烈的感兴趣的信号。 在这种情况下，自适应滤波器偏置电流可能会降低，从而降低本底噪声并降低互调，从而降低功耗，因为强信号可以容忍更高的噪声和失真。 当RSSI电平低并且AGC增益高时，存在弱信号，低噪声模式可以通过增加用于降低本底噪声的滤波器的偏置电流来实现，但互调效应仍然可以被允许，因此可以切割这些滤波器 背部。 其他案例得到支持。 可以基于相对RSSI和AGC电平动态地改变RSSI和AGC增益电平门限。
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7.发明授权Method and apparatus for implementing power line communications over a DC power supply cable 有权通过直流电源电缆实现电力线通信的方法和装置公开(公告)号：US09391452B1
公开(公告)日：2016-07-12
申请号：US13449633
申请日：2012-04-18
CPC分类号： H02J1/00 , H02J1/06 , H02J13/0003 , H02J13/0024 , H04B3/54 , H04B13/00
摘要： Devices and systems for providing reduced cost and increased reliability power line communications (PLC) and electrical power to a network device using a PLC supply unit via a single cable with 2 wires are disclosed. The PLC supply unit receives a PLC power and data signal, extracts the power signal, the data signal and generates a timing signal based on the power signal. The PLC supply converts the electrical power signal from an alternating current (AC) to a direct current (DC) electrical power signal and then recombines the DC electrical power signal with the data signal and the timing signal and sends the composite signal to the network device. The network device receives the composite signal and uses the DC electrical power signal to power the network device and, at an internal PLC processing module, processes the data signal for communication with other network devices using the timing data.
摘要翻译： 公开了一种用于通过具有2根电线的单根电缆，使用PLC供电单元为网络设备降低成本和提高可靠性的电力线通信（PLC）和电力的设备和系统。 PLC供电单元接收PLC电源和数据信号，提取电源信号，数据信号，并根据电源信号生成定时信号。 PLC电源将电力信号从交流（AC）转换为直流（DC）电力信号，然后将直流电功率信号与数据信号和定时信号重新组合，并将复合信号发送到网络设备 。 网络设备接收复合信号，并使用直流电功率信号为网络设备供电，并且在内部PLC处理模块处理数据信号，以使用定时数据与其他网络设备进行通信。
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8.发明授权公开(公告)号：US08149065B1
公开(公告)日：2012-04-03
申请号：US13088645
申请日：2011-04-18
申请人： Randy Tsang , Yu-chi Lee , David Cousinard
发明人： Randy Tsang , Yu-chi Lee , David Cousinard
IPC分类号： H03L7/085
摘要： A phase-locked loop that supports a large frequency drift capability, yet maintains a low Kvco, and does not introduce noise or discontinuities in the frequency of the generated phase-locked loop output signal. The phase-locked loop may include a VCO with an LC tank circuit, the capacitance of which may be adjusted in incremental units. By gradually adjusting a control signal applied to a selected VCO LC tank circuit frequency adjustment control line, e.g., in a continuous ramped function, or time-averaged ramped function, from LOW-to-HIGH or from HIGH-to-LOW, over a period of time that is greater than the response time of the phase-locked loop, a frequency range supported by the VCO may be shifted to either a higher frequency range or a lower frequency range, as needed, to accommodate environmentally induced frequency drift in the VCO, without introducing noise or discontinuities in the frequency of the generated phase-locked loop output signal.
摘要翻译： 一个锁相环，支持大的频率漂移能力，但维持低的Kvco，并且不会在产生的锁相环输出信号的频率中引入噪声或不连续性。 锁相环可以包括具有LC槽电路的VCO，其电容可以以增量单位调节。 通过逐渐调整施加到所选择的VCO LC电路频率调节控制线的控制信号，例如，以连续斜坡功能或时间平均斜坡函数，从低到高或从高到低，通过 时间段大于锁相环的响应时间，由VCO支持的频率范围可以根据需要转换到更高的频率范围或更低的频率范围，以适应环境中的频率漂移 VCO，不会在产生的锁相环输出信号的频率中引入噪声或不连续性。
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9.发明授权公开(公告)号：US07940129B1
公开(公告)日：2011-05-10
申请号：US12431195
申请日：2009-04-28
申请人： Randy Tsang , Yu-chi Lee , David Cousinard
发明人： Randy Tsang , Yu-chi Lee , David Cousinard
IPC分类号： H03L7/085
摘要： A phase-locked loop that supports a large frequency drift capability, yet maintains a low Kvco, and does not introduce noise or discontinuities in the frequency of the generated phase-locked loop output signal. The phase-locked loop may include a VCO with an LC tank circuit, the capacitance of which may be adjusted in incremental units. By gradually adjusting a control signal applied to a selected VCO LC tank circuit frequency adjustment control line, e.g., in a continuous ramped function, or time-averaged ramped function, from LOW-to-HIGH or from HIGH-to-LOW, over a period of time that is greater than the response time of the phase-locked loop, a frequency range supported by the VCO may be shifted to either a higher frequency range or a lower frequency range, as needed, to accommodate environmentally induced frequency drift in the VCO, without introducing noise or discontinuities in the frequency of the generated phase-locked loop output signal.
摘要翻译： 一个锁相环，支持大的频率漂移能力，但维持低的Kvco，并且不会在产生的锁相环输出信号的频率中引入噪声或不连续性。 锁相环可以包括具有LC槽电路的VCO，其电容可以以增量单位调节。 通过逐渐调整施加到所选择的VCO LC电路频率调节控制线的控制信号，例如，以连续斜坡功能或时间平均斜坡函数，从低到高或从高到低，通过 时间段大于锁相环的响应时间，由VCO支持的频率范围可以根据需要转换到更高的频率范围或更低的频率范围，以适应环境中的频率漂移 VCO，不会在产生的锁相环输出信号的频率中引入噪声或不连续性。
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公开(公告)号：US08462887B1
公开(公告)日：2013-06-11
申请号：US13213846
申请日：2011-08-19
申请人： King Chun Tsai , Patrick Clement , David Cousinard
发明人： King Chun Tsai , Patrick Clement , David Cousinard
IPC分类号： H04L27/00
CPC分类号： H03M3/458 , H01L51/524 , H03M1/004 , H03M1/12
摘要： A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.
摘要翻译： 提出了包括调谐器电路和转换器电路的接收器。 调谐器电路提供对应于在所选频道上接收的调制信号的模拟信号。 转换器电路包括采样时钟，该采样时钟用于以与采样时钟的频率对应的转换速率将模拟信号转换为数字信号。 采样时钟可在至少两个不同的时钟频率之间选择。
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