公开(公告)号：US20050017282A1

公开(公告)日：2005-01-27

申请号：US10604488

申请日：2003-07-25

申请人： David Dobuzinsky ,  Jonathan Faltermeier ,  Philip Flaitz ,  Rajarao Jammy ,  Yuko Ninomiya ,  Ravikumar Ramachandran ,  Viraj Sardesai ,  Yun Wang

发明人： David Dobuzinsky ,  Jonathan Faltermeier ,  Philip Flaitz ,  Rajarao Jammy ,  Yuko Ninomiya ,  Ravikumar Ramachandran ,  Viraj Sardesai ,  Yun Wang

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L29/66181

摘要： In the process of forming a trench capacitor, the conductive strap connecting the center electrode of the capacitor with a circuit element in the substrate, such as the pass transistor of a DRAM cell, is separated from the crystalline substrate material by a barrier layer of silicon carbide formed during the process of etching the material within the trench, such as an oxide collar, using a reactive ion etch process with an etchant gas that contains carbon, such as C4F8.

摘要翻译： 在形成沟槽电容器的过程中，将电容器的中心电极与衬底中的电路元件（例如DRAM单元的传输晶体管）连接的导电带通过硅的阻挡层与晶体衬底材料分离 在蚀刻沟槽内的材料（例如氧化物环）的过程中形成的碳化物，其使用具有包含碳的蚀刻剂气体如C4F8的反应离子蚀刻工艺。

公开(公告)号：US06504210B1

公开(公告)日：2003-01-07

申请号：US09599484

申请日：2000-06-23

申请人： Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Jack A. Mandelman ,  Viraj Sardesai ,  Mary Elizabeth Weybright

发明人： Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Jack A. Mandelman ,  Viraj Sardesai ,  Mary Elizabeth Weybright

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/28044 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66553

摘要： A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.

摘要翻译： 提供了一种完全多晶硅封装的含金属镶嵌栅极结构，可用于千兆DRAM（动态随机存取存储器）器件。 完全封装的含金属的镶嵌栅极包括具有形成在所述基板的表面部分上的栅极氧化层的半导体基板; 形成在所述栅极氧化物层上的栅极多晶硅层; 形成在所述多晶硅层上的金属层; 以及形成在所述金属层上的帽氧化层，其中所述金属层被所述多晶硅和氧化物层完全包封。 镶嵌栅极结构还可以包括形成在所述栅极多晶硅层上的多晶硅间隔物，并且所述金属层被封装在其中，并且外部多晶硅侧壁被氧化。

公开(公告)号：US06268293B1

公开(公告)日：2001-07-31

申请号：US09442956

申请日：1999-11-18

申请人： Lawrence Clevenger ,  Greg Costrini ,  Dave Dobuzinsky ,  Yoichi Otani ,  Thomas Rupp ,  Viraj Sardesai

发明人： Lawrence Clevenger ,  Greg Costrini ,  Dave Dobuzinsky ,  Yoichi Otani ,  Thomas Rupp ,  Viraj Sardesai

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

摘要翻译： 在集成电路芯片中形成导线的镶嵌方法。 通过在50-400mTorr的压力下以500至3000瓦的电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2-30sccm的C 4 F 8，20-80sccm的CO，2-30sccm的O 2和50-400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：US20070249133A1

公开(公告)日：2007-10-25

申请号：US11308604

申请日：2006-04-11

申请人： Gary Bronner ,  David Fried ,  Jeffrey Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Sardesai

发明人： Gary Bronner ,  David Fried ,  Jeffrey Gambino ,  Leland Chang ,  Ramachandra Divakaruni ,  Haizhou Yin ,  Gregory Costrini ,  Viraj Sardesai

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.

摘要翻译： 一种在半导体器件上形成导电间隔物的方法。 该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层 。 任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

公开(公告)号：US5401677A

公开(公告)日：1995-03-28

申请号：US173313

申请日：1993-12-23

申请人： Robert D. Bailey ,  Cyril Cabral, Jr. ,  Brian Cunningham ,  Hormazdyar M. Dalal ,  James M. Harper ,  Viraj Sardesai ,  Horatio S. Wildman ,  Thomas O. Williams

发明人： Robert D. Bailey ,  Cyril Cabral, Jr. ,  Brian Cunningham ,  Hormazdyar M. Dalal ,  James M. Harper ,  Viraj Sardesai ,  Horatio S. Wildman ,  Thomas O. Williams

IPC分类号： C23C14/16 ,  C23C14/58 ,  H01L21/285 ,  H01L21/44 ,  H01L21/48

CPC分类号： C23C14/165 ,  C23C14/58 ,  H01L21/28518 ,  Y10S438/906

摘要： An improved process for the formation of high quality, high yield platinum silicides on silicon wafers uses a post sputter platinum deposition and high vacuum bake to complete the first step of silicide reaction, resulting in Pt.sub.2 Si formation before sinter. This additional process step is then followed by a 500.degree. to 900.degree. C. sinter. The use of a high vacuum bake provides easy control of O.sub.2 and H.sub.2 O impurities. The vacuum bake can be done in any high vacuum tool. The bake temperatures range from 200.degree. to 450.degree. C. at 5.times.10.sup.-6 torr, with an in-situ bake time of 3 to 5 minutes or an ex-situ bake time of 10 to 30 minutes, depending on batch size or tool. A particular advantage of the process is that it can be performed in existing tools.

摘要翻译： 在硅晶片上形成高质量，高产量的铂硅化物的改进方法使用后溅镀铂沉积和高真空烘烤来完成硅化物反应的第一步骤，从而在烧结之前形成Pt 2 Si。 然后再加入500〜900℃的烧结体。 使用高真空烘烤可以方便地控制O2和H2O杂质。 真空烘烤可以在任何高真空工具中进行。 焙烧温度范围为200〜450℃，5×10 -6乇，原位烘烤时间为3〜5分钟，或者异位烘烤时间为10〜30分钟，这取决于批量或工具。 该过程的一个特别优点是可以在现有工具中执行。