公开(公告)号：US06642090B1

公开(公告)日：2003-11-04

申请号：US10063994

申请日：2002-06-03

申请人： David M. Fried ,  Edward J. Nowak ,  Beth A Rainey ,  Devendra K. Sadana

发明人： David M. Fried ,  Edward J. Nowak ,  Beth A Rainey ,  Devendra K. Sadana

IPC分类号： H01L218238

CPC分类号： H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

摘要： The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

摘要翻译： 因此，本发明提供了克服现有技术的许多缺点的用于形成鳍状场效应晶体管（FET）的器件结构和方法。 具体地，器件结构和方法提供了从批量半导体晶片形成finFET器件的能力，同时提供改进的晶片到晶片器件的均匀性。 具体地说，该方法有助于从散装半导体晶片形成finFET器件，从而改进翅片高度控制。 此外，该方法提供了从散装半导体形成finFET的能力，同时提供散热片之间的隔离以及各个finFET的源极和漏极区域之间的隔离。 最后，该方法还可以提供翅片宽度的优化。 因此，本发明的器件结构和方法提供均匀的finFET制造的优点，同时使用成本效应的体晶片。

公开(公告)号：US06657261B2

公开(公告)日：2003-12-02

申请号：US09757317

申请日：2001-01-09

申请人： Fariborz Assaderaghi ,  Tze-chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Fariborz Assaderaghi ,  Tze-chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L29/78603

摘要： A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

公开(公告)号：US07645650B2

公开(公告)日：2010-01-12

申请号：US11774663

申请日：2007-07-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

IPC分类号： H01L21/84

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

摘要翻译： 一种形成晶体管的方法。 提供半导体衬底。 图案化半导体衬底以提供第一本体边缘。 在第一身体边缘附近提供第一费米能级的第一门结构。 图案化半导体衬底以提供第二本体边缘。 半导体衬底的第一和第二主体边缘限定晶体管体。 在第二身体边缘附近设置第二费米能级的第二门结构。 在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

公开(公告)号：US20090134463A1

公开(公告)日：2009-05-28

申请号：US12348344

申请日：2009-01-05

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： H01L29/78

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

摘要翻译： 一种半导体结构和用于制造集成电路芯片的系统。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。 用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

公开(公告)号：US07517806B2

公开(公告)日：2009-04-14

申请号：US11186748

申请日：2005-07-21

申请人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

发明人： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

IPC分类号： H01L21/302

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US07288445B2

公开(公告)日：2007-10-30

申请号：US11125063

申请日：2005-05-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

IPC分类号： H01L21/84

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

摘要翻译： 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：US07163851B2

公开(公告)日：2007-01-16

申请号：US10227995

申请日：2002-08-26

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： H01L21/84

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： The present invention provides methods for fabrication of fin-type field effect transistors (FinFETs) and thick-body devices on the same chip using common masks and steps to achieve greater efficiency than prior methods. The reduction in the number of masks and steps is achieved by using common masks and steps with several scaling strategies. In one embodiment, the structure normally associated with a FinFET is created on the side of a thick silicon mesa, the bulk of which is doped to connect with a body contact on the opposite side of the mesa. The invention also includes FinFETs, thick-body devices, and chips fabricated by the methods.

摘要翻译： 本发明提供了使用公共掩模和步骤在相同芯片上制造鳍式场效应晶体管（FinFET）和厚体器件的方法，以实现比现有方法更高的效率。 通过使用具有多种缩放策略的常用掩模和步骤来实现掩模和步骤数量的减少。 在一个实施例中，通常与FinFET相关联的结构产生在厚硅台面的一侧，该厚硅台面的大部分被掺杂以与台面的相对侧上的身体接触连接。 本发明还包括FinFET，厚体器件和通过这些方法制造的芯片。

公开(公告)号：US07064413B2

公开(公告)日：2006-06-20

申请号：US10774773

申请日：2004-02-09

申请人： David M. Fried ,  Edward J. Nowak

发明人： David M. Fried ,  Edward J. Nowak

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/00 ,  H01L27/108

CPC分类号： H01L28/20 ,  H01L27/0802 ,  H01L29/0657 ,  H01L29/785 ,  H01L29/8605 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substrate; implanting dopant ions into the exposed vertical surfaces of the at least one semiconductor body off-axis at a concentration and energy sufficient to penetrate into the exposed vertical surfaces of the at least one semiconductor body without saturation; and forming contacts to the at least one semiconductor body. The present invention is directed to a Fin structure which includes a resistor present within the thin vertically oriented semiconductor body.

公开(公告)号：US07060553B2

公开(公告)日：2006-06-13

申请号：US11216862

申请日：2005-08-31

申请人： David M. Fried ,  Edward J. Nowak

发明人： David M. Fried ,  Edward J. Nowak

IPC分类号： H01L21/8242

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/785

摘要： Device designs and methods are described for incorporating capacitors commonly used in planar CMOS technology into a FinFET based technology. A capacitor includes at least one single-crystal Fin structure having a top surface and a first side surface opposite a second side surface. Adjacent the top surface of the at least one Fin structure is at least one insulator structure. Adjacent the at least one insulator structure and over a portion of the at least one Fin structure is at least one conductor structure. Decoupling capacitors may be formed at the circuit device level using simple design changes within the same integration method, thereby allowing any number, combination, and/or type of decoupling capacitors to be fabricated easily along with other devices on the same substrate to provide effective decoupling capacitance in an area-efficient manner with superior high-frequency response.

摘要翻译： 描述了器件设计和方法，用于将平面CMOS技术中通常使用的电容纳入到基于FinFET的技术中。 电容器包括至少一个单晶鳍结构，其具有顶表面和与第二侧表面相对的第一侧表面。 邻近至少一个鳍结构的顶表面是至少一个绝缘体结构。 与至少一个绝缘体结构相邻并且至少一个鳍结构的一部分上方是至少一个导体结构。 去耦电容器可以在相同的集成方法中使用简单的设计变化在电路器件级形成，从而允许任何数量，组合和/或类型的去耦电容器与同一衬底上的其它器件一起容易地制造，以提供有效的去耦 电容以区域有效的方式具有出色的高频响应。

公开(公告)号：US08598683B2

公开(公告)日：2013-12-03

申请号：US13451087

申请日：2012-04-19

申请人： David M. Fried ,  Edward J. Nowak

发明人： David M. Fried ,  Edward J. Nowak

IPC分类号： H01L29/93

CPC分类号： H01L29/93

摘要： A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

摘要翻译： 半导体结构包括具有第一极性的第一区域和与第一区域相邻的第二极性的第二区域的半导体衬底; 以及第一端子，包括：位于所述第一区域中的第一深沟槽，与所述第一深沟槽的侧壁的上部和所述第一深沟槽的底部相邻的第一节点电介质; 第一导电内电极，位于第一节点电介质的内部，并由第一节点电介质与第一区域电绝缘; 以及将第一导电内电极电耦合到第一区域的第一电接触。