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    Process for PECVD of silicon oxide using TEOS decomposition
    1.
    发明授权
    Process for PECVD of silicon oxide using TEOS decomposition 失效

    公开(公告)号：US4892753A

    公开(公告)日：1990-01-09

    申请号：US262993

    申请日：1988-10-26

    申请人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    发明人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC分类号： C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  C23C16/54 ,  H01L21/314 ,  H01L21/316

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    CVD of silicon oxide using TEOS decomposition and in-situ planarization process
    2.
    发明授权
    CVD of silicon oxide using TEOS decomposition and in-situ planarization process 失效
    使用TEOS分解和原位平面化处理的氧化硅CVD

    公开(公告)号：US4872947A

    公开(公告)日：1989-10-10

    申请号：US262992

    申请日：1988-10-26

    申请人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    发明人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC分类号： C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  C23C16/54 ,  H01L21/314 ,  H01L21/316

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either along or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    摘要翻译： 公开了一种高压，高通量，单晶片，半导体处理反应器，其能够通过溅射单独地或作为一部分的溅射进行热CVD，等离子体增强CVD，等离子体辅助回蚀，等离子体自清洁和沉积形貌修饰 原位多步处理。 还公开了用于形成高度保形二氧化硅层的低温CVD工艺。 该过程使用非常高的室压和低温，以及TEOS和臭氧反应物。 低温CVD二氧化硅沉积步骤特别可用于平坦化下面的阶梯介电层，或者沿着或结合随后的各向同性蚀刻。 用于形成平坦化的二氧化硅层的优选的原位多步骤方法使用（1）在低温和高压下高速二氧化硅沉积，随后（2）也在高压下沉积保形二氧化硅层，以及 低温，随后（3）高速各向同性蚀刻，优选在低温和高压下，在用于两个氧化物沉积步骤的相同反应器中。 公开了用于不同应用的步骤的各种组合，优选的反应器自清洁步骤也是如此。

    Plasma-enhanced CVD process using TEOS for depositing silicon oxide
    3.
    发明授权
    Plasma-enhanced CVD process using TEOS for depositing silicon oxide 失效

    公开(公告)号：US5362526A

    公开(公告)日：1994-11-08

    申请号：US645999

    申请日：1991-01-23

    申请人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    发明人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC分类号： C23C16/48 ,  C23C16/04 ,  C23C16/40 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C23C16/46 ,  C23C16/50 ,  C23C16/509 ,  C23C16/54 ,  C23F4/00 ,  C30B25/14 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/683 ,  B05D3/06

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process
    5.
    发明授权
    Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process 失效

    公开(公告)号：US06167834A

    公开(公告)日：2001-01-02

    申请号：US07928642

    申请日：1992-08-13

    申请人： David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    发明人： David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC分类号： C23C1600

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, the TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    Process for PECVD of silicon oxide using TEOS decomposition
    9.
    再颁专利
    Process for PECVD of silicon oxide using TEOS decomposition 失效

    公开(公告)号：USRE36623E

    公开(公告)日：2000-03-21

    申请号：US752972

    申请日：1996-12-02

    申请人： David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    发明人： David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC分类号： C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  C23C16/54 ,  H01L21/314 ,  H01L21/316 ,  H05H1/24

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surface. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the sane reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.