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    Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods
    3.
    再颁专利
    Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods 有权
    通过这些方法形成的薄碳化硅外延层和半导体器件的接触方法

    公开(公告)号：USRE42423E1

    公开(公告)日：2011-06-07

    申请号：US12266739

    申请日：2008-11-07

    申请人： Martin E. Kordesch ,  Howard D. Bartlow ,  Richard L. Woodin

    发明人： Martin E. Kordesch ,  Howard D. Bartlow ,  Richard L. Woodin

    IPC分类号： H01L29/737 ,  H01L21/331

    CPC分类号： H01L29/732 ,  H01L21/0485 ,  H01L29/0649 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/74

    摘要： Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

    摘要翻译： 提供了一种用于形成化合物半导体器件的接触件的方法，而不会使器件电短路。 在一个实施例中，高掺杂的化合物半导体材料通过相反导电类型的化合物半导体材料的开口与相同导电类型的化合物半导体材料电连接。 另一实施例公开了一种包括多个化合物半导体层的晶体管，其中高掺杂的化合物半导体材料通过相反导电类型的化合物半导体层中的开口与相同导电类型的化合物半导体层电连接。 实施例还包括电连接到高掺杂化合物半导体材料的金属触点。 公开了一种基本上平面的半导体器件。 在实施方案中，化合物半导体材料可以是碳化硅。

    High power semiconductor device having bolt-down ceramic platform
    6.
    发明授权
    High power semiconductor device having bolt-down ceramic platform 失效
    具有螺栓式陶瓷平台的大功率半导体器件

    公开(公告)号：US5949649A

    公开(公告)日：1999-09-07

    申请号：US67703

    申请日：1998-04-28

    申请人： Howard D. Bartlow

    发明人： Howard D. Bartlow

    IPC分类号： H01L23/40 ,  H05K7/20

    CPC分类号： H01L23/4006 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2924/0002

    摘要： A power semiconductor device package in which a semiconductor chip is mounted on a ceramic platform and sealed thereon by a lid. The platform has opposing end portions which receive fasteners for directly fastening the platform and semiconductor device to a heat sink without the requirement of a separate mounting clamp. In one embodiment, metal films are provided on a surface of the platform adjacent to recesses for receiving the fasteners. The metal films function to distribute the stress of the fasteners over the surface of the end portions thereby minimizing the possibility of fracture of the ceramic platform.

    摘要翻译： 一种功率半导体器件封装，其中半导体芯片安装在陶瓷平台上并通过盖子密封在其上。 平台具有相对的端部，其接收用于将平台和半导体器件直接固定到散热器的紧固件，而不需要单独的安装夹具。 在一个实施例中，金属膜设置在邻近凹槽的平台的表面上，用于接收紧固件。 金属膜用于将紧固件的应力分布在端部部分的表面上，从而最小化陶瓷平台断裂的可能性。

    Venetian blind cell layout for RF power transistor
    7.
    发明授权
    Venetian blind cell layout for RF power transistor 失效
    用于射频功率晶体管的威尼斯盲电池布局

    公开(公告)号：US5414296A

    公开(公告)日：1995-05-09

    申请号：US236312

    申请日：1994-05-02

    申请人： Howard D. Bartlow

    发明人： Howard D. Bartlow

    IPC分类号： H01L23/482 ,  H01L29/417 ,  H01L29/423 ,  H01L29/72

    CPC分类号： H01L29/42304 ,  H01L23/4824 ,  H01L29/41708 ,  H01L2924/0002 ,  Y10S257/923

    摘要： Operating characteristics of an electronics device in which alternating currents flow are improved by reducing positive electromagnetic coupling between currents. This is accomplished by altering the direction of a current flow to obtain negative coupling through current flow in the same direction, or by minimizing electromagnetic coupling through perpendicular current flow, or by increasing the spacing between two electromagnetically coupled currents. In a bipolar transistor structure a feed structure for emitter and base current includes wire bonding pads aligned so that emitter current and base current flow to wire bonding pads perpendicular to the direction of collector current flow and with adjacent emitter currents and base currents flowing in the same direction. Each feed structure includes a plurality of interdigitated fingers for contacting emitter and base regions, all emitter and base currents in said interdigitated fingers of all feed structures flowing in the same direction as the collector.

    摘要翻译： 通过减少电流之间的正电磁耦合来改善交流电流流动的电子设备的工作特性。 这是通过改变电流的方向以通过沿相同方向的电流流动获得负耦合，或者通过使通过垂直电流流动的电磁耦合最小化，或通过增加两个电磁耦合电流之间的间隔来实现的。 在双极晶体管结构中，用于发射极和基极电流的馈电结构包括引线接合焊盘，引线键合焊盘对准，使得发射极电流和基极电流流向垂直于集电极电流方向的引线键合焊盘，并且相邻的发射极电流和基极电流流过 方向。 每个馈送结构包括用于接触发射极和基极区域的多个交叉指状物，所有馈送结构的所述交叉指状物中的所有发射极和基极电流在与收集器相同的方向上流动。

    Method of thermal balancing RF power transistor array
    10.
    发明授权
    Method of thermal balancing RF power transistor array 失效
    RF功率晶体管阵列的热平衡方法

    公开(公告)号：US5023189A

    公开(公告)日：1991-06-11

    申请号：US519136

    申请日：1990-05-04

    申请人： Howard D. Bartlow

    发明人： Howard D. Bartlow

    IPC分类号： H01L23/52

    CPC分类号： H01L23/52 ,  H01L24/49 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/3011 ,  Y10T29/49004

    摘要： Thermal balance in an array of RF transistor cells in which all transistors are connected in parallel is obtained by interconnecting the transistors to array contacts by means of discrete wire leads. The array is electrically tested and a temperature distribution in the array is obtained. Thereafter, the wire leads are varied in length and height above the plane of the array to improve temperature distribution during test. The steps are repeated as necessary to obtain a desired temperature balance in the array.

    摘要翻译： 其中所有晶体管并联连接的RF晶体管单元阵列中的热平衡通过使用分立导线将晶体管与阵列触点互连而获得。 该阵列被电测试并且获得阵列中的温度分布。 此后，导线的长度和高度在阵列的平面之上变化，以改善测试期间的温度分布。 根据需要重复这些步骤以获得阵列中期望的温度平衡。