Instruction and Logic for a Logical Move in an Out-Of-Order Processor
    1.
    发明申请
    Instruction and Logic for a Logical Move in an Out-Of-Order Processor 有权
    用于在乱序处理器中逻辑移动的指令和逻辑

    公开(公告)号:US20150277911A1

    公开(公告)日:2015-10-01

    申请号:US14229179

    申请日:2014-03-28

    IPC分类号: G06F9/30

    摘要: A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

    摘要翻译: 处理器包括具有用于接收逻辑移动指令的逻辑的分配单元。 逻辑移动指令包括作为源参数的源逻辑寄存器和作为目的地参数的目的地逻辑寄存器。 源逻辑寄存器被分配给源物理寄存器,目的地逻辑寄存器被分配给目的物理寄存器。 分配单元包括将源逻辑寄存器的第一值分配给目的地逻辑寄存器并且在将第一值分配给目的地逻辑寄存器之前和之后维持目的物理寄存器的第二值的逻辑。

    Vibrating Sorting Table
    2.
    发明申请

    公开(公告)号:US20180029075A1

    公开(公告)日:2018-02-01

    申请号:US15225348

    申请日:2016-08-01

    申请人: Raul Martinez

    发明人: Raul Martinez

    IPC分类号: B06B1/02 B23P19/04

    摘要: A vibrating sorting table for separating loosely attached parts from a workpiece includes a bench. The bench comprises a bottom. Each of a plurality of supports is coupled to and extends substantially vertically from a respective edge of the bottom. A top is flexibly coupled to each of the supports. The top is substantially parallel to the bottom. The top is movable relative to the supports and the bottom. A pair of rims is coupled singly to opposing sides of the top. The rims separate a workpiece positioned on the bench from an upper face of the top. A vibration unit is coupled to a lower face of the top. The vibration unit is positioned to impart vibrational forces to the top, such that the workpiece coupled to the top vibrates. Parts of the workpiece that are loosely attached separate from the workpiece and fall to the upper face of the top.

    PARTIAL COMMITS IN DYNAMIC BINARY TRANSLATION BASED SYSTEMS
    3.
    发明申请
    PARTIAL COMMITS IN DYNAMIC BINARY TRANSLATION BASED SYSTEMS 有权
    基于动态二进制翻译的系统的部分组合

    公开(公告)号:US20150007153A1

    公开(公告)日:2015-01-01

    申请号:US13929360

    申请日:2013-06-27

    IPC分类号: G06F9/45 G06F11/14

    CPC分类号: G06F8/443 G06F8/4434

    摘要: Described herein are technologies for optimizing computer code. A code generator can optimize a portion of original code to create optimized code. The code generator can create a partial commit point to indicate that execution of the optimized code produces an invalid architectural state. The code generator can create recovery information recover a valid architectural state at a recovery point. The code generator can associate the partial commit point and recovery information with the optimized code.

    摘要翻译: 这里描述的是用于优化计算机代码的技术。 代码生成器可以优化原始代码的一部分以创建优化的代码。 代码生成器可以创建部分提交点,以指示优化代码的执行产生无效的架构状态。 代码生成器可以创建恢复信息,以在恢复点恢复有效的体系结构状态。 代码生成器可以将部分提交点和恢复信息与优化的代码相关联。

    IDENTIFICATION AND MANAGEMENT OF UNSAFE OPTIMIZATIONS
    9.
    发明申请
    IDENTIFICATION AND MANAGEMENT OF UNSAFE OPTIMIZATIONS 有权
    不安全优化的认定与管理

    公开(公告)号:US20140282451A1

    公开(公告)日:2014-09-18

    申请号:US13977118

    申请日:2013-03-15

    IPC分类号: G06F9/45

    CPC分类号: G06F8/443 G06F9/4552

    摘要: Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed runtime environment (MRE) executed by a processing device, a notice of misprediction of optimized code, the misprediction occurring during a runtime of the optimized code, determining, by the MRE, whether a local misprediction counter (LMC) associated with a code region of the optimized code causing the misprediction exceeds a local misprediction threshold (LMT) value, and when the LMC exceeds the LMT value, compiling, by the MRE, native code of the optimized code to generate a new version of the optimized code, wherein the code region in the new version of the optimized code is not optimized.

    摘要翻译: 公开了实现不安全优化的识别和管理的技术。 本公开的方法包括:通过由处理设备执行的管理运行时环境(MRE)接收优化代码的错误预测的通知,在优化代码的运行时间期间发生的错误预测,由MRE确定本地 与优化代码的代码区域相关联的误预测计数器(LMC)导致错误预测超过局部误预测阈值(LMT)值,当LMC超过LMT值时,由MRE编译优化代码的本机代码以生成 新版本的优化代码,其中新版本的优化代码中的代码区域未被优化。