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    Method and apparatus for controlling power management state transitions between devices connected via a clock forwarded interface
    1.
    发明授权
    Method and apparatus for controlling power management state transitions between devices connected via a clock forwarded interface 有权
    用于控制经由时钟转发接口连接的设备之间的电源管理状态转换的方法和装置

    公开(公告)号：US06446215B1

    公开(公告)日：2002-09-03

    申请号：US09378026

    申请日：1999-08-20

    申请人： Derrick R. Meyer ,  Scott A. White ,  Michael T. Clark ,  Philip E. Madrid

    发明人： Derrick R. Meyer ,  Scott A. White ,  Michael T. Clark ,  Philip E. Madrid

    IPC分类号： G06F126

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3253 ,  G06F13/405 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

    摘要： A method and apparatus for controlling power management state transitions between two devices, e.g., a processor and a bus bridge, that are connected through a clock forwarded interface bus in a computer system. The bus bridge is configured to coordinate disconnection of the processor from the interface. Particularly, the bus bridge may use a fist signal to indicate whether or not the processor is to be disconnected from the interface (e.g. a CONNECT signal) and the processor may use a second signal to indicate whether or not the processor is to be disconnected from the interface (e.g. a PROCREADY signal). The processor is disconnected from the interface responsive to both the first signal and the second signal indicating that the processor is to be disconnected. The signals may also be used to reconnect the processor to the interface.

    摘要翻译： 一种用于控制通过计算机系统中的时钟转发接口总线连接的两个设备（例如处理器和总线桥）之间的功率管理状态转换的方法和装置。 总线桥被配置为协调处理器与接口的断开连接。 特别地，总线桥可以使用第一信号来指示处理器是否与接口断开连接（例如，连接信号），并且处理器可以使用第二信号来指示处理器是否被断开 接口（例如PROCREADY信号）。 所述处理器响应于所述第一信号和所述第二信号指示所述处理器将被断开而与所述接口断开连接。 信号也可用于将处理器重新连接到接口。

    Core redundancy in a chip multiprocessor for highly reliable systems
    2.
    发明授权
    Core redundancy in a chip multiprocessor for highly reliable systems 有权
    用于高可靠性系统的芯片多处理器的核心冗余

    公开(公告)号：US07328371B1

    公开(公告)日：2008-02-05

    申请号：US10966466

    申请日：2004-10-15

    申请人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Philip E. Madrid ,  Scott A. White ,  Ajay Naini

    发明人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Philip E. Madrid ,  Scott A. White ,  Ajay Naini

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1641 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/184 ,  G06F2201/845

    摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor cores to other devices in a computer system. The node controller comprises a circuit coupled to receive the communications from the processor cores. In a redundant execution mode in which at least a first processor core is redundantly executing code that a second processor core is also executing, the circuit is configured to compare communications from the first processor core to communications from the second processor core to verify correct execution of the code. In some embodiments, the processor cores and the node controller may be integrated onto a single integrated circuit chip as a CMP. A similar method is also contemplated.

    摘要翻译： 在一个实施例中，节点包括多个处理器核和耦合到处理器核的节点控制器。 节点控制器被配置为将来自处理器核心的通信路由到计算机系统中的其他设备。 节点控制器包括耦合以从处理器核心接收通信的电路。 在冗余执行模式中，其中至少第一处理器核冗余地执行第二处理器核也正在执行的代码，该电路被配置为将来自第一处理器核心的通信与来自第二处理器核心的通信进行比较，以验证是否正确执行 代码。 在一些实施例中，处理器核心和节点控制器可以作为CMP集成到单个集成电路芯片上。 也可以考虑类似的方法。

    System and method for operating components of an integrated circuit at independent frequencies and/or voltages
    3.
    发明授权
    System and method for operating components of an integrated circuit at independent frequencies and/or voltages 有权
    用于在独立频率和/或电压下操作集成电路的组件的系统和方法

    公开(公告)号：US07263457B2

    公开(公告)日：2007-08-28

    申请号：US11325054

    申请日：2006-01-03

    申请人： Scott A. White ,  William A. Hughes ,  Philip E. Madrid

    发明人： Scott A. White ,  William A. Hughes ,  Philip E. Madrid

    IPC分类号： G01K1/08

    CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

    摘要： Multiple logic cores of integrated circuits and processors may be configured to operate at frequencies and voltages independently of each other. Additionally, other components, such as a common bridge configured to interface with the logic cores, may operate at a voltage and frequency independent of the voltage and frequency at which the logic cores are operating. The operating frequency and/or voltage of a logic core may be independently adjusted for various reasons, including power management and temperature control. Logic circuitry at an interface between the controller and the logic cores may translate logic signals from one voltage and/or frequency to another to enable communication between the bridge and the logic core when the two are operating at different voltages and/or frequencies.

    摘要翻译： 集成电路和处理器的多个逻辑核可以被配置为在彼此独立的频率和电压下工作。 此外，其他组件，例如被配置为与逻辑内核接口的公共桥可以在与逻辑核运行的电压和频率无关的电压和频率下工作。 可以由于各种原因（包括电源管理和温度控制）独立地调整逻辑核的工作频率和/或电压。 控制器和逻辑核心之间的接口处的逻辑电路可以将逻辑信号从一个电压和/或频率转移到另一个电压和/或频率，以便当两个电路和/或频率在不同的电压和/或频率下工作时，实现桥与逻辑核之间的通信。

    Alternate fault handler
    6.
    发明授权
    Alternate fault handler 有权
    备用故障处理程序

    公开(公告)号：US06442707B1

    公开(公告)日：2002-08-27

    申请号：US09430120

    申请日：1999-10-29

    申请人： Kevin J. McGrath ,  Michael T. Clark ,  Scott A. White

    发明人： Kevin J. McGrath ,  Michael T. Clark ,  Scott A. White

    IPC分类号： H02H305

    CPC分类号： G06F9/3861 ,  G06F9/32

    摘要： In a processor a reorder buffer maintains a load/store (LS) fault address register (LSFAR). When the processor's load/store unit reports most LS exceptions, the reorder buffer redirects the microcode unit of the processor to execute a fault handler indicated by an address stored in the LSFAR. The LSFAR may be mapped into the register space of the processor. It may be written by a microcode routine with the address of a specific fault handler at the beginning of a microcode routine or at any time during a microcode routine. As the reorder buffer retires instructions it checks for writes to the LSFAR. If one exists, the reorder buffer loads the result data of that write into the LSFAR. In a preferred embodiment the reorder buffer retires instructions in program order and the LSFAR is not updated speculatively. Also, in a preferred embodiment, when a microcode routine exits, the LSFAR is automatically returned to a default value which indicates a generic fault handling routine.

    摘要翻译： 在处理器中，重排序缓冲器维护加载/存储（LS）故障地址寄存器（LSFAR）。 当处理器的加载/存储单元报告大多数LS异常时，重排序缓冲区重定向处理器的微代码单元，以执行由存储在LSFAR中的地址指示的故障处理程序。 LSFAR可以映射到处理器的寄存器空间。 微代码程序可以在微代码程序的开始处或在微代码程序中的任何时间由具有特定故障处理程序的地址的微代码程序写入。 当重新排序缓冲区退出指令时，它会检查对LSFAR的写入。 如果存在，则重新排序缓冲区将该写入的结果数据加载到LSFAR中。 在优选实施例中，重新排序缓冲器以程序顺序退出指令，LSFAR不被推测更新。 此外，在优选实施例中，当微代码例程退出时，LSFAR自动返回到指示通用故障处理例程的默认值。

    Multi-core integrated circuit with shared debug port
    7.
    发明授权
    Multi-core integrated circuit with shared debug port 有权
    具有共享调试端口的多核集成电路

    公开(公告)号：US07665002B1

    公开(公告)日：2010-02-16

    申请号：US11302942

    申请日：2005-12-14

    申请人： Scott A. White ,  Michael T. Clark ,  Timothy J. Wood

    发明人： Scott A. White ,  Michael T. Clark ,  Timothy J. Wood

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318583 ,  G01R31/31705 ,  G06F11/267 ,  G06F11/3656

    摘要： A single test access port, such as a JTAG-based debug port may be utilized to perform debug operations on logic cores of a multi-core integrated circuit, such as a multi-core processor. The shared debug port may respond to a particular command to enter a debugging mode and may be configured to forward all commands and data to a debugging controller of the integrated circuit during debugging. A mask register may be used to indicate which logic cores of the multi-core integrated circuit should be debugged. Additionally, custom debugging commands may include mask or core select fields to indicate which logic cores should be affected by the particular command. Debugging mode may be initialized for one or more logic cores either externally, such as be asserted a DBREQ signal, or internally, such as by configuring one or more breakpoints.

    摘要翻译： 可以使用诸如基于JTAG的调试端口的单个测试访问端口来执行诸如多核处理器的多核集成电路的逻辑核的调试操作。 共享调试端口可以响应特定命令进入调试模式，并且可以配置为在调试期间将所有命令和数据转发到集成电路的调试控制器。 可以使用掩码寄存器来指示应该调试多核集成电路的哪些逻辑核心。 此外，自定义调试命令可以包括掩码或核心选择字段，以指示特定命令应该影响哪些逻辑核心。 可以在外部对一个或多个逻辑核心初始化调试模式，例如断言DBREQ信号，或内部，例如通过配置一个或多个断点。

    Method and apparatus for fault handling in computer systems
    9.
    发明授权
    Method and apparatus for fault handling in computer systems 有权
    计算机系统中故障处理的方法和装置

    公开(公告)号：US06625726B1

    公开(公告)日：2003-09-23

    申请号：US09587114

    申请日：2000-06-02

    申请人： Michael T. Clark ,  Scott A. White

    发明人： Michael T. Clark ,  Scott A. White

    IPC分类号： G06F944

    CPC分类号： G06F9/30101 ,  G06F9/30174 ,  G06F9/3842 ,  G06F9/3863

    摘要： A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first register may be updated during the execution of an instruction. A second register may be used to store an address previously first register. The contents of the second register may be kept unchanged until the retirement of the instruction that is currently executing. If a fault occurs during execution of the instruction, a microcode fault handler may perform routines that may clear the fault or those conditions which led to the fault. The microcode fault handler may also copy the contents of the second register back into the first register. Execution of the instruction may be restarted from the operation just prior to when the fault occurred. The program from which the instruction originated may then continue to run. The first and second registers may be general purpose registers in some embodiments, while special purpose registers may be used in other embodiments.

    摘要翻译： 一种计算机系统中故障处理的方法和装置。 在一个实施例中，第一寄存器用于存储指向堆栈顶部的地址。 存储在第一寄存器中的地址可以在执行指令期间被更新。 第二寄存器可以用于存储先前首先寄存器的地址。 第二寄存器的内容可以保持不变，直到当前执行的指令退出。 如果在执行指令期间发生故障，则微代码故障处理程序可能会执行可能会清除故障或导致故障的条件的例程。 微代码故障处理器还可以将第二寄存器的内容复制回第一寄存器。 可以在发生故障之前的操作中重新启动指令的执行。 然后可以继续运行指令发起的程序。 在一些实施例中，第一和第二寄存器可以是通用寄存器，而在其它实施例中可以使用专用寄存器。

    Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor
    10.
    发明授权
    Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor 有权
    在更新微处理器中寄存器的一部分时，合并窄寄存器以分辨数据依赖性

    公开(公告)号：US06493819B1

    公开(公告)日：2002-12-10

    申请号：US09442209

    申请日：1999-11-16

    申请人： Eric W. Mahurin ,  Scott A. White ,  Michael T. Clark

    发明人： Eric W. Mahurin ,  Scott A. White ,  Michael T. Clark

    IPC分类号： G06F930

    CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： A microprocessor includes general purpose registers which may be accessed or updated in portions. Dependencies may be created between an instruction which updates only a portion of a destination register and a subsequent instruction which requires a larger portion of that destination register, inclusive of the smaller updated portion, as a source. To resolve such dependencies between instructions, a determination is made upon decode of an instruction whether it updates only a portion of a destination or the entire destination. If only a portion of the destination is updated by the instruction, a read of the destination is done prior to execution of the instruction and the data read from the destination is merged with the results of the instruction execution. The merged data is then conveyed as the results of the instruction execution.

    摘要翻译： 微处理器包括可以部分访问或更新的通用寄存器。 可以在只更新目的地寄存器的一部分的指令和需要该目的地寄存器的较大部分（包括较小的更新部分）作为源的后续指令之间产生依赖性。 为了解决指令之间的这种依赖性，在解码指令时是否仅更新目的地或整个目的地的一部分进行确定。 如果只有目的地的一部分被指令更新，则在执行指令之前完成目的地的读取，并且从目的地读取的数据与指令执行的结果合并。 然后将合并的数据作为指令执行的结果传送。