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1.发明授权
公开(公告)号：US4937050A
公开(公告)日：1990-06-26
申请号：US216133
申请日：1988-07-07
申请人： Dieter Meinecke , Rainer Van Rijckevorsel , Manfred Pauli , Rudolf Schussler , Thomas Jack , Dieter Knoll
发明人： Dieter Meinecke , Rainer Van Rijckevorsel , Manfred Pauli , Rudolf Schussler , Thomas Jack , Dieter Knoll
CPC分类号： G01N21/8483 , G01N2021/478
摘要： According to a second aspect, the present invention also provides an apparatus for the evaluation of a flat test carrier for the analytical determination of components of a body fluid, said apparatus having a measurement unit and a positioning means, by means of which the test carrier is positioned and firmly held in a measurement position in such a manner that its test field is present in a definite position with regard to the measurement unit, wherein, for the evaluation of test carriers with a covering layer fixed in the manner of a flap on one edge of the test carrier, there is present a shutter element with a contact surface for pressing on the covering layer, the aperture element and/or the positioning means being mounted and operable in such a manner that the contact surface in the last phase of approaching the covering layer makes, relative to the test carrier, a tilting movement about a tilting axis which lies in close proximity to a fixing edge of the covering layer.
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2.发明授权
公开(公告)号：US4780283A
公开(公告)日：1988-10-25
申请号：US619016
申请日：1984-06-11
申请人： Dieter Meinecke , Rainer Van Rijckevorsel , Manfred Pauli , Rudolf Schussler , Thomas Jack , Dieter Knoll
发明人： Dieter Meinecke , Rainer Van Rijckevorsel , Manfred Pauli , Rudolf Schussler , Thomas Jack , Dieter Knoll
CPC分类号： G01N21/8483 , G01N2021/478
摘要： According to a first aspect, the present invention provides an apparatus for the evaluation of a longitudinally extending, flexible test carrier for the analytical determination of components of a body fluid. The test carrier has an insertion end to be inserted into the apparatus and a handling end. The test carrier is positioned and securely held in a measurement position in such a manner that its test field is present in a definite position with regard to the measurement unit. The positioning element includes at least two holding elements, one of which firmly holds the test carrier close to its insertion end and the other of which firmly holds the test carrier close to its handling end. A supporting surface being provided on which the test carrier lies at least partly in its measurement position. According to a second aspect for the evaluation of test carriers with a covering layer fixed in the manner of a flap on one edge of the test carrier, there is present a shutter element with a contact surface for pressing on the covering layer, the aperture element being mounted and operable in such a manner that the contact surface in the last phase of approaching the covering layer makes, relative to the test carrier, a tilting movement about a tilting axis which lies in close proximity to a fixing edge of the covering layer.
摘要翻译： 根据第一方面，本发明提供了一种用于评估纵向延伸的柔性测试载体的装置，用于分析测定体液的组分。 测试托架具有插入到装置中的插入端和处理端。 测试载体被定位并牢固地保持在测量位置，使得其测试场相对于测量单元存在于确定的位置。 定位元件包括至少两个保持元件，其中之一牢固地保持测试托架靠近其插入端，而另一个固定元件将测试托架牢牢地保持在其操作端附近。 设置有支撑表面，测试载体至少部分地位于测量位置上。 根据第二方面的用于评价具有以测试载体的一个边缘上的翼片的方式固定的覆盖层的测试载体，存在具有用于在覆盖层上按压的接触表面的快门元件，孔径元件 以使接近覆盖层的最后阶段的接触表面相对于测试载体相对于位于覆盖层的固定边缘附近的倾斜轴线的倾斜运动的方式安装和操作。
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3.发明授权Cmos-compatible lateral dmos transistor and method for producing such a transistor 失效Cmos兼容横向晶体管及其制造方法公开(公告)号：US06878995B2
公开(公告)日：2005-04-12
申请号：US10239933
申请日：2001-03-24
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/78 , H01L21/335
CPC分类号： H01L29/66659 , H01L29/0615 , H01L29/1033 , H01L29/7835
摘要： A CMOS-compatible DMOS transistor can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-μm production technology for CMOS circuits. A gate insulator of the transistor is of a unitary thickness under a control gate in the entire (active) region through which current flows. A zone of increased doping concentration (well region) which is near the surface and which determines the transistor threshold voltage is so arranged under the control gate that it occupies the entire area under the control gate which is on the active region and ends within a so-called drift space between the control gate and a highly doped drain region. The entire surface of the drift space is covered by a zone of the conductivity type of the drain region (VLDD), which is lowly doped in comparison with the highly doped drain region.
摘要翻译： 可以通过适当的布局配置来设计CMOS兼容的DMOS晶体管，用于非常高的漏极电压或在非常高的频率下进行功率放大，并且可以以与常规子母线相比低的额外成本来生产CMOS兼容的DMOS晶体管 CMOS电路的生产技术。 在电流流过的整个（有源）区域中，晶体管的栅极绝缘体在控制栅极下方具有整体厚度。 靠近表面并确定晶体管阈值电压的增加的掺杂浓度（阱区）的区域被布置在控制栅极下方，其占据位于有源区上的控制栅极下方的整个区域并且结束于其中 在控制栅极和高掺杂漏极区之间的偏移漂移空间。 漂移空间的整个表面由漏区（VLDD）的导电类型的区域覆盖，其与高掺杂漏极区相比被低掺杂。
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4.发明授权
公开(公告)号：US5393391A
公开(公告)日：1995-02-28
申请号：US728768
申请日：1991-07-08
IPC分类号： G01N27/28 , G01N27/403 , G01N27/416 , G01N33/483 , G01N27/30
CPC分类号： G01N27/4035 , G01N27/4165
摘要： The present invention provides an electrode arrangement for the electrochemical analysis of components of a liquid, having a base body (7; 53; 85; 103; 139; 155; 175; 193), made of an insulating material with at least one measurement electrode (21; 57; 89; 111; 143; 157; 195) held on the base body, adapted to be brought into phase boundary contact with the liquid to be analysed, said measurement electrode being selective for a predetermined kind of ion in the liquid, and with at least one reference electrode (19; 55; 87; 109; 141; 153; 173; 197; 199) held on the base body and adapted to be brought into phase boundary contact, together with the measurement electrode, with the liquid, wherein the base body carries a removable closure part (45; 61; 91; 107; 137; 163; 187; 203) which, together with the base body, forms a closed hollow chamber (11; 52; 86; 104; 135; 159; 177; 201), the closed hollow chamber containing a standard electrolyte, especially one containing the predetermined kind of ion, defining, with the ion-selective measurement electrode, a predetermined half cell potential, said standard electrolyte being in phase boundary contact not only with the or each measurement electrode but also with the or each reference electrode.
摘要翻译： 本发明提供了一种用于电化学分析液体组分的电极装置，其具有由具有至少一个测量电极的绝缘材料制成的基体（7; 53; 85; 103; 139; 155; 175; 193） （21; 57; 89; 111; 143; 157; 195），其保持在所述基体上，适于与所述待分析液体相界接触，所述测量电极对于所述液体中的预定种类的离子是选择性的 以及保持在基体上并适于与测量电极一起进入相界接触的至少一个参考电极（19; 55; 87; 109; 141; 153; 173; 197; 199） 液体，其中所述基体携带可移除的封闭部分（45; 61; 91; 107; 137; 163; 187; 203），所述可拆卸闭合部分与所述基体一起形成封闭的中空室（11; 52; 86; 104; 135; 159; 177; 201），封闭的中空室含有标准电解质，特别是含有预定类型的电解质 的离子，用离子选择性测量电极限定预定的半电池电位，所述标准电解质不仅与测量电极或每个测量电极相位边界地接触，而且与所述或每个参比电极相接触。
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公开(公告)号：US08035167B2
公开(公告)日：2011-10-11
申请号：US12448032
申请日：2007-12-07
申请人： Dieter Knoll , Bernd Heinemann , Karl-Ernst Ehwald
发明人： Dieter Knoll , Bernd Heinemann , Karl-Ernst Ehwald
IPC分类号： H01L27/015
CPC分类号： H01L27/0623 , H01L21/82285 , H01L21/8249 , H01L27/0826
摘要： A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.
摘要翻译： 一种互补双极性半导体器件（CBi半导体器件），包括第一导电类型的衬底，衬底中的有源双极晶体管区域，其中垂直双极晶体管的基极，发射极和集电极被布置，垂直外延基极npn双极晶体管 有源双极晶体管区域的第一子集，有源双极晶体管区域的第二子集中的垂直外延基极pnp双极晶体管，分别布置成邻接有源双极晶体管区域的集电极接触区域和分别横向 界定有源双极性晶体管区域和集电极接触区域，其中一方面被布置在一方面的有源双极性晶体管区域的第一或第二或第二子集之间，另一方面相邻的集电极接触区域是 相应的浅场绝缘区域为第一 在基板内部的方向上具有第一深度方向的第一类型，并且第二类型的浅的场绝缘区域比有源双极晶体管区域的第一深度方向的第二较深的深度方向的区域限定有源双极晶体管区域和集电极接触区域 横截面在彼此背离的一侧。
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公开(公告)号：US20100019326A1
公开(公告)日：2010-01-28
申请号：US12448032
申请日：2007-12-07
申请人： Dieter Knoll , Bernd Heinemann , Karl-Ernst Ehwald
发明人： Dieter Knoll , Bernd Heinemann , Karl-Ernst Ehwald
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L27/0623 , H01L21/82285 , H01L21/8249 , H01L27/0826
摘要： A complementary bipolar semiconductor device (CBi semiconductor device) comprising a substrate of a first conductivity type, active bipolar transistor regions in the substrate, in which the base, emitter and collector of vertical bipolar transistors are arranged, vertical epitaxial-base npn bipolar transistors in a first subset of the active bipolar transistor regions, vertical epitaxial-base pnp bipolar transistors in a second subset of the active bipolar transistor regions, collector contact regions which are respectively arranged adjoining an active bipolar transistor region, and shallow field insulation regions which respectively laterally delimit the active bipolar transistor regions and the collector contact regions, wherein arranged between the first or the second or both the first and also the second subset of active bipolar transistor regions on the one hand and the adjoining collector contact regions on the other hand is a respective shallow field insulation region of a first type with a first depthwise extent in the direction of the substrate interior and shallow field insulation regions of a second type of a second greater depthwise extent than the first depthwise extent of the active bipolar transistor regions delimit the active bipolar transistor regions and collector contact regions viewed in cross-section at their sides facing away from each other.
摘要翻译： 一种互补双极性半导体器件（CBi半导体器件），包括第一导电类型的衬底，衬底中的有源双极晶体管区域，其中垂直双极晶体管的基极，发射极和集电极被布置，垂直外延基极npn双极晶体管 有源双极晶体管区域的第一子集，有源双极晶体管区域的第二子集中的垂直外延基极pnp双极晶体管，分别布置成邻接有源双极晶体管区域的集电极接触区域和分别横向 界定有源双极性晶体管区域和集电极接触区域，其中一方面被布置在一方面的有源双极性晶体管区域的第一或第二或第二子集之间，另一方面相邻的集电极接触区域是 相应的浅场绝缘区域为第一 在基板内部的方向上具有第一深度方向的第一类型，并且第二类型的第二类型的浅的场绝缘区域比有源双极性晶体管区域的第一深度方向的第二较深的深度方向的区域限定了观察到的有源双极晶体管区域和集电极接触区域 横截面在彼此背离的一侧。
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公开(公告)号：US06465318B1
公开(公告)日：2002-10-15
申请号：US09787571
申请日：2001-08-02
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L29/7322
摘要： This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.
摘要翻译： 本发明涉及双极晶体管及其制造方法。 本发明的任务是提出一种双极晶体管及其制造方法，其消除了用于制造基底的具有差分外延的简单多晶硅技术的常规布置的缺点， 双极晶体管的速度特性，以在金属触点和有源（内部）晶体管区域之间产生高导电连接以及最小化的无源晶体管表面，同时避免任何额外的工艺复杂性和增加的接触电阻。 本发明解决了通过创建合适的外延工艺条件的工作，多晶硅层以比有源晶体管区中的外延层更大的厚度沉积在绝缘体区上。 与外延层相比，多晶硅层的厚度越大，通过使用非常低的温度来沉积一部分或整个缓冲层来实现。 使用低温进行沉积允许绝缘体层的更好的成核和减少沉积的空闲时间。 与有源晶体管区域相比，这允许在绝缘体层上实现更大的厚度。
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公开(公告)号：US07595534B2
公开(公告)日：2009-09-29
申请号：US10433969
申请日：2001-12-06
申请人： Bernd Heinemann , Karl-Ernst Ehwald , Dieter Knoll , Bernd Tillack , Dirk Wolansky , Peter Schley
发明人： Bernd Heinemann , Karl-Ernst Ehwald , Dieter Knoll , Bernd Tillack , Dirk Wolansky , Peter Schley
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/74 , H01L21/26506 , H01L21/823807 , H01L21/823892 , H01L29/1083
摘要： The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate (2) with one or more buried high-carbon Si layers (3) under an epitaxial layer and with the Si cap layer (4), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.
摘要翻译： 本发明涉及衬底晶片中的层。 本发明的目的是提供衬底晶片中的层，其中克服了常规组件的缺点，以便一方面实现具有相对较低成本的高度缩放的数字CMOS电路中的闩锁的适当电阻，以及 另一方面，为了确保模拟高频电路的低衬底损耗/耦合，此外，以非破坏性的方式影响组件行为。 为此，本发明提供了在具有一个或多个掩埋的高碳Si层（3）的外延层和Si覆盖层（4）下的高电阻p-Si衬底（2）中的注入剂量， 与传统的基板晶片相比，通过抑制掺杂剂扩散以及在补偿注入缺陷时产生缺陷而用于逆向槽型材，从而实现了谷电阻的降低，最后增加了电阻 闭锁
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9.发明授权Method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip 失效在芯片上制造高速垂直npn双极晶体管和互补MOS晶体管的方法公开(公告)号：US07205188B2
公开(公告)日：2007-04-17
申请号：US10450006
申请日：2001-12-06
申请人： Dieter Knoll , Bernd Heinemann
发明人： Dieter Knoll , Bernd Heinemann
IPC分类号： H01L21/8238
CPC分类号： H01L21/8249
摘要： The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.
摘要翻译： 本发明涉及在芯片上制造高速垂直npn双极晶体管和互补MOS晶体管的方法。 为了在芯片上生产这些高速垂直npn双极晶体管和互补MOS晶体管，所有技术方法步骤用于在npn双极晶体管的有源区中产生集电极，基极和发射极的垂直结构以及横向 构成集电极区域之前，在产生用于MOS晶体管的槽和栅极绝缘层之前执行基极区域和发射极区域。
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公开(公告)号：US20050023642A1
公开(公告)日：2005-02-03
申请号：US10496531
申请日：2002-12-02
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/1004 , H01L29/7325
摘要： The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.
摘要翻译： 根据本发明的半导体器件包括衬底，限定半导体衬底的有源区域的场绝缘区域，集电极，与集电极相关联的至少一个集电极接触区域以及具有相关联的基极连接区域的基极。 集电极和集电极接触区形成在相同的有源区中。 此外，基极连接区部分地延伸在有源区上方并且通过绝缘体层与有源区的表面分离。
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