摘要:
Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.
摘要:
A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.
摘要:
A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.
摘要:
A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
摘要:
A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
摘要:
A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
摘要:
A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
摘要:
A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
摘要:
Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.