公开(公告)号：US20070048983A1

公开(公告)日：2007-03-01

申请号：US11498693

申请日：2006-08-03

申请人： Do-Young Kim ,  Jong-man Kim ,  Ji-sim Jung ,  Takashi Noguchi ,  Jang-yeon Kwon

发明人： Do-Young Kim ,  Jong-man Kim ,  Ji-sim Jung ,  Takashi Noguchi ,  Jang-yeon Kwon

IPC分类号： H01L21/265

CPC分类号： H01L21/02381 ,  C23C14/165 ,  C23C14/5813 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02631

摘要： A method of fabricating a high-quality silicon thin layer includes making Xe ions generated by RF power collide with a silicon target material layer to generate silicon particles from the silicon target material layer; and depositing the silicon particles on a predetermined substrate. The method is performed under a pressure of about 5 mTorr or lower and at an RF power of about 200 W or more. In this method, the silicon thin layer is thermally stabilized, and the amount of gas captured in silicon crystals during the sputtering process is greatly reduced.

摘要翻译： 制造高质量硅薄层的方法包括使由RF功率产生的Xe离子与硅靶材料层碰撞，从硅靶材料层产生硅颗粒; 并将硅颗粒沉积在预定的衬底上。 该方法在约5mTorr或更低的压力和约200W或更高的RF功率下进行。 在该方法中，硅薄层被热稳定化，并且溅射过程中在硅晶体中捕获的气体量大大降低。

公开(公告)号：US20060270097A1

公开(公告)日：2006-11-30

申请号：US11440249

申请日：2006-05-24

申请人： Do-young Kim ,  Takashi Noguchi ,  Jang-yeon Kwon ,  Jong-man Kim ,  Ji-sim Jung

发明人： Do-young Kim ,  Takashi Noguchi ,  Jang-yeon Kwon ,  Jong-man Kim ,  Ji-sim Jung

IPC分类号： H01L21/00

CPC分类号： H01L27/1229 ,  H01L27/1214 ,  H01L27/1274 ,  H01L27/3244 ,  H01L29/04

摘要： An organic light emitting display includes: a substrate; a plurality of pixels which are arranged in a matrix on the substrate, each pixel having a switching transistor, a driving transistor, and an organic light emission diode (OLED). Silicon channels in the switching transistor have lower carrier mobility than silicon channels in the driving transistor. The low carrier mobility of amorphous silicon in the switching transistor prevents current leakage and the higher carrier mobility of polycrystalline silicon in the driving transistor provides a high driving speed and an extended lifetime.

摘要翻译： 有机发光显示器包括：基板; 在衬底上以矩阵形式布置的多个像素，每个像素具有开关晶体管，驱动晶体管和有机发光二极管（OLED）。 开关晶体管中的硅沟道具有比驱动晶体管中的硅沟道更低的载流子迁移率。 开关晶体管中的非晶硅的低载流子迁移率防止电流泄漏，并且驱动晶体管中的多晶硅的较高的载流子迁移率提供高的驱动速度和延长的寿命。

公开(公告)号：US20060284179A1

公开(公告)日：2006-12-21

申请号：US11455559

申请日：2006-06-19

申请人： Ji-sim Jung ,  Do-Young Kim ,  Jong-man Kim ,  Jang-yeon Kwon ,  Takashi Noguchi

发明人： Ji-sim Jung ,  Do-Young Kim ,  Jong-man Kim ,  Jang-yeon Kwon ,  Takashi Noguchi

IPC分类号： H01L29/04

CPC分类号： H01L29/78603 ,  H01L29/66757

摘要： A silicon thin film transistor (“TFT”) and method of manufacturing the same are provided where the silicon TFT includes buffer layers deposited on both surfaces of a substrate, respectively, and a silicon channel is deposited on one of the buffer layers. A gate insulator is deposited on the silicon channel, and a gate is deposited on the gate insulator. Because of the buffer layers deposited on both surfaces of the substrate, the bending of the substrate is prevented and the silicon TFT has good operating performance.

摘要翻译： 提供硅薄膜晶体管（“TFT”）及其制造方法，其中硅TFT分别包括沉积在衬底的两个表面上的缓冲层，并且硅沟道沉积在缓冲层之一上。 栅极绝缘体沉积在硅沟道上，栅极沉积在栅极绝缘体上。 由于沉积在衬底的两个表面上的缓冲层，防止了衬底的弯曲，并且硅TFT具有良好的操作性能。

公开(公告)号：US08058094B2

公开(公告)日：2011-11-15

申请号：US12707115

申请日：2010-02-17

申请人： Takashi Noguchi ,  Jong-man Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Ji-sim Jung ,  Hyuck Lim

发明人： Takashi Noguchi ,  Jong-man Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Ji-sim Jung ,  Hyuck Lim

IPC分类号： H01L21/00

CPC分类号： H01L29/78645 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/78624 ,  H01L29/78696

摘要： A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.

摘要翻译： 晶体管包括： 至少两个多晶硅层基本上彼此平行地布置，每个多晶硅层包括沟道区和至少两个设置在沟道区相对侧的高导电性区; 对应于两个多晶硅层的沟道区并与两个多晶硅层交叉的栅极和介于栅极和两个多晶硅层之间的栅极绝缘层，其中低导电性区域邻近 并且形成在每个多晶硅层的沟道区域和一个高导电率区域之间。

公开(公告)号：US07700954B2

公开(公告)日：2010-04-20

申请号：US11621627

申请日：2007-01-10

申请人： Takashi Noguchi ,  Jong-man Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Ji-sim Jung ,  Hyuck Lim

发明人： Takashi Noguchi ,  Jong-man Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Ji-sim Jung ,  Hyuck Lim

IPC分类号： H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00

CPC分类号： H01L29/78645 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/78624 ,  H01L29/78696

摘要： A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.

摘要翻译： 晶体管包括： 至少两个多晶硅层基本上彼此平行地布置，每个多晶硅层包括沟道区和至少两个设置在沟道区相对侧的高导电性区; 对应于两个多晶硅层的沟道区并与两个多晶硅层交叉的栅极和介于栅极和两个多晶硅层之间的栅极绝缘层，其中低导电性区域邻近 并且形成在每个多晶硅层的沟道区域和一个高导电率区域之间。

公开(公告)号：US07563659B2

公开(公告)日：2009-07-21

申请号：US11003326

申请日：2004-12-06

申请人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

发明人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

IPC分类号： H01L21/00

CPC分类号： H01L21/02532 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02354 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/31608 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

摘要： A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using inductively coupled plasma chemical vapor deposition (ICP-CVD). After the ICP-CVD, excimer laser annealing (ELA) is performed while increasing energy by predetermined steps. A poly-Si active layer and a SiO2 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 Å or more. An interface trap density of the SiO2 can be as high as 1011/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

摘要翻译： 提供一种制造多晶硅薄膜的方法和使用其制造多晶硅TFT的方法。 使用电感耦合等离子体化学气相沉积（ICP-CVD）在低温下形成多晶硅薄膜。 在ICP-CVD之后，在通过预定步骤增加能量的同时进行准分子激光退火（ELA）。 使用ICP-CVD在约150℃的温度下沉积多晶硅有源层和SiO 2栅极绝缘层。 多晶硅的大晶粒尺寸约为3000或更大。 SiO2的界面陷阱密度高达1011 / cm2。 具有良好电特性的晶体管可以在低温下制造，因此可以形成在耐热塑料基板上。

公开(公告)号：US20090298268A1

公开(公告)日：2009-12-03

申请号：US12457586

申请日：2009-06-16

申请人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

发明人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

IPC分类号： H01L21/336 ,  H01L21/205

CPC分类号： H01L21/02532 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02354 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/31608 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

摘要： A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and a Si02 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 A or more. An interface trap density of the Si02 can be as high as lo∥/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

摘要翻译： 提供一种制造多晶硅薄膜的方法和使用其制造多晶硅TFT的方法。 使用ICP-CVD在低温下形成多晶硅薄膜。 在ICP-CVD之后，在通过预定步骤增加能量的同时执行ELA。 使用ICP-CVD在约150℃的温度下沉积多晶硅有源层和SiO 2栅极绝缘层。 多晶硅具有约3000A以上的大晶粒尺寸。 SiO 2的界面陷阱密度可以高达lo // / cm2。 具有良好电特性的晶体管可以在低温下制造，因此可以形成在耐热塑料基板上。

公开(公告)号：US20060008957A1

公开(公告)日：2006-01-12

申请号：US11003326

申请日：2004-12-06

申请人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

发明人： Jang-yeon Kwon ,  Min-koo Han ,  Se-young Cho ,  Kyung-bae Park ,  Do-young Kim ,  Min-cheol Lee ,  Sang-myeon Han ,  Takashi Noguchi ,  Young-soo Park ,  Ji-sim Jung

IPC分类号： H01L21/205

CPC分类号： H01L21/02532 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02354 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02686 ,  H01L21/2026 ,  H01L21/31608 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

摘要： A method of fabricating a poly-Si thin film and a method of fabricating a poly-Si TFT using the same are provided. The poly-Si thin film is formed at a low temperature using ICP-CVD. After the ICP-CVD, ELA is performed while increasing energy by predetermined steps. A poly-Si active layer and a SiO2 gate insulating layer are deposited at a temperature of about 150° C. using ICP-CVD. The poly-Si has a large grain size of about 3000 Å or more. An interface trap density of the SiO2 can be as high as 1011/cm2. A transistor having good electrical characteristics can be fabricated at a low temperature and thus can be formed on a heat tolerant plastic substrate.

摘要翻译： 提供一种制造多晶硅薄膜的方法和使用其制造多晶硅TFT的方法。 使用ICP-CVD在低温下形成多晶硅薄膜。 在ICP-CVD之后，在通过预定步骤增加能量的同时执行ELA。 使用ICP-CVD在约150℃的温度下沉积多晶硅有源层和SiO 2/2栅极绝缘层。 多晶硅的大晶粒尺寸约为3000或更大。 SiO 2 2的界面陷阱密度可以高达10-11 / cm 2。 具有良好电特性的晶体管可以在低温下制造，因此可以形成在耐热塑料基板上。

公开(公告)号：US07439197B2

公开(公告)日：2008-10-21

申请号：US11267264

申请日：2005-11-07

申请人： Jang-yeon Kwon ,  Hyuk Lim ,  Takashi Noguchi ,  Young-soo Park ,  Suk-pil Kim ,  Hans S. Cho ,  Ji-sim Jung ,  Kyung-bae Park ,  Do-young Kim

发明人： Jang-yeon Kwon ,  Hyuk Lim ,  Takashi Noguchi ,  Young-soo Park ,  Suk-pil Kim ,  Hans S. Cho ,  Ji-sim Jung ,  Kyung-bae Park ,  Do-young Kim

IPC分类号： H01L21/00 ,  C30B23/00

CPC分类号： H01L29/66765 ,  C23C14/3464 ,  C23C14/46 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02631

摘要： A method of preparing a semiconductor film on a substrate is disclosed. The method includes arranging an insulating substrate in a deposition chamber and depositing a semiconductor film onto the insulating substrate using ion beam deposition, wherein a temperature of the insulating substrate during the depositing does not exceed 250° C. The method can produce a thin film transistor. The disclosed ion beam deposition method forms, at lower temperature and with low impurities, a film morphology with desired smoothness and grain size. Deposition of semiconductor films on low melting point substrates, such as plastic flexible substrates, is enables.

摘要翻译： 公开了一种在衬底上制备半导体膜的方法。 该方法包括在沉积室中布置绝缘衬底，并使用离子束沉积将半导体膜沉积到绝缘衬底上，其中沉积期间绝缘衬底的温度不超过250℃。该方法可以产生薄膜晶体管 。 所公开的离子束沉积方法在较低温度和低杂质下形成具有所需光滑度和晶粒尺寸的膜形态。 能够在诸如塑料柔性基底的低熔点基底上沉积半导体膜。

公开(公告)号：US20060220034A1

公开(公告)日：2006-10-05

申请号：US11369947

申请日：2006-03-08

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim ,  Ji-sim Jung ,  Jang-yeon Kwon

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim ,  Ji-sim Jung ,  Jang-yeon Kwon

IPC分类号： H01L33/00

CPC分类号： H01L29/66757 ,  H01L29/4908

摘要： A thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor may include a substrate, a buffer layer, a polysilicon layer, a gate insulating layer and/or a gate electrode, and a capping layer. The buffer layer may be formed on the substrate. The polysilicon layer may be formed on the buffer layer, and may include a first doped region, a second doped region, and a channel region. The gate insulating layer and a gate electrode may be sequentially stacked on the channel region of the polysilicon layer. The capping layer may be stacked on the gate electrode.

摘要翻译： 一种薄膜晶体管及其制造方法。 薄膜晶体管可以包括衬底，缓冲层，多晶硅层，栅极绝缘层和/或栅电极以及覆盖层。 缓冲层可以形成在衬底上。 多晶硅层可以形成在缓冲层上，并且可以包括第一掺杂区域，第二掺杂区域和沟道区域。 栅极绝缘层和栅电极可以顺序堆叠在多晶硅层的沟道区上。 覆盖层可以堆叠在栅电极上。