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    MEMS relay and method of forming the MEMS relay
    1.
    发明授权
    MEMS relay and method of forming the MEMS relay 有权
    MEMS继电器和形成MEMS继电器的方法

    公开(公告)号：US08378766B2

    公开(公告)日：2013-02-19

    申请号：US13020052

    申请日：2011-02-03

    申请人： Dok Won Lee ,  Peter Johnson ,  Aditi Dutt Chaudhuri

    发明人： Dok Won Lee ,  Peter Johnson ,  Aditi Dutt Chaudhuri

    IPC分类号： H01H51/22

    CPC分类号： H01L29/84 ,  H01H1/0036 ,  H01H49/00 ,  H01H50/005 ,  H01H50/36 ,  H01H50/44 ,  Y10T29/49073

    摘要： A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits.

    摘要翻译： 微机电系统（MEMS）继电器包括具有通过间隙彼此垂直分离的第一接触区域和第二接触区域的开关。 MEMS继电器需要小的垂直运动来封闭间隙，因此机械稳健。 此外，MEMS继电器占地面积小，因此可以形成在小型集成电路之上。

    Method of making a controlled seam laminated magnetic core for high frequency on-chip power inductors
    7.
    发明授权
    Method of making a controlled seam laminated magnetic core for high frequency on-chip power inductors 有权
    制造用于高频片上功率电感器的可控缝层压磁芯的方法

    公开(公告)号：US08314676B1

    公开(公告)日：2012-11-20

    申请号：US13098656

    申请日：2011-05-02

    申请人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

    发明人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

    IPC分类号： H01F5/00 ,  H01F7/06 ,  H01L27/08

    CPC分类号： H01F17/0033 ,  H01F41/046 ,  Y10T29/4902 ,  Y10T29/49075 ,  Y10T29/49078

    摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.

    摘要翻译： 可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。 受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层层叠件具有水平底座以及从底座基本垂直向上延伸的第一和第二间隔开的侧壁，以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

    METHOD OF MAKING A CONTROLLED SEAM LAMINATED MAGNETIC CORE FOR HIGH FREQUENCY ON-CHIP POWER INDUCTORS
    8.
    发明申请
    METHOD OF MAKING A CONTROLLED SEAM LAMINATED MAGNETIC CORE FOR HIGH FREQUENCY ON-CHIP POWER INDUCTORS 有权
    制造用于高频片上功率电感器的受控海绵层压磁芯的方法

    公开(公告)号：US20120280781A1

    公开(公告)日：2012-11-08

    申请号：US13098656

    申请日：2011-05-02

    申请人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

    发明人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

    IPC分类号： H01F27/24 ,  H01F41/02

    CPC分类号： H01F17/0033 ,  H01F41/046 ,  Y10T29/4902 ,  Y10T29/49075 ,  Y10T29/49078

    摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.

    摘要翻译： 可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。 受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层片具有水平底座和第一和第二间隔开的侧壁，从侧面基本垂直向上延伸以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

    Method and system for forming a capacitive micromachined ultrasonic transducer
    9.
    发明授权
    Method and system for forming a capacitive micromachined ultrasonic transducer 有权
    用于形成电容微加工超声换能器的方法和系统

    公开(公告)号：US08222065B1

    公开(公告)日：2012-07-17

    申请号：US12587139

    申请日：2009-10-02

    申请人： Peter Smeys ,  Peter Johnson ,  Gokhan Percin

    发明人： Peter Smeys ,  Peter Johnson ,  Gokhan Percin

    IPC分类号： H01L29/72

    CPC分类号： B06B1/0292 ,  H01L27/0688

    摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide features. For a particular embodiment, the SOI wafer comprises a single crystal epitaxial layer, a buried oxide layer and a silicon layer, and the single crystal epitaxial layer is bonded to the planarized oxide features, after which the silicon layer and the buried oxide layer of the SOI wafer are removed, leaving the single crystal epitaxial layer bonded to the oxide layer.

    摘要翻译： 提供一种用于形成电容微加工超声换能器（CMUT）的方法，其包括在硅晶片中的CMUT控制芯片外部形成氧化物特征。 氧化物的特征被平坦化。 绝缘体上硅（SOI）晶片与平坦化的氧化物特征结合。 对于特定实施例，SOI晶片包括单晶外延层，掩埋氧化物层和硅层，并且单晶外延层结合到平坦化的氧化物特征，之后硅层和掩埋氧化物层 去除SOI晶片，留下单晶外延层与氧化物层结合。

    Method of Batch Trimming Circuit Elements
    10.
    发明申请
    Method of Batch Trimming Circuit Elements 有权
    批量修剪电路元件的方法

    公开(公告)号：US20120161294A1

    公开(公告)日：2012-06-28

    申请号：US12978492

    申请日：2010-12-24

    申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

    发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

    IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/66

    CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/0802 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

    摘要翻译： 在每个晶片被形成为包括暴露高精度电路的电路内部的可调节电路元件的开口的过程中，每个具有多个高精度电路和相应的微调控制电路的多个晶片被批量修整。 高精度电路和微调控制电路在修整阶段通过沿着锯木街道行进的金属轨迹进行电激活。 该方法将晶片接触结构连接到每个晶片以电激活金属迹线。 该方法将具有晶片接触结构的晶片放置在当高精度电路的实际输出电压与高精度电路的预测输出电压不匹配时，暴露的可调节电路元件被电镀或阳极化的解决方案中。