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    Method and system for forming a capacitive micromachined ultrasonic transducer
    1.
    发明授权
    Method and system for forming a capacitive micromachined ultrasonic transducer 有权
    用于形成电容微加工超声换能器的方法和系统

    公开(公告)号：US08222065B1

    公开(公告)日：2012-07-17

    申请号：US12587139

    申请日：2009-10-02

    申请人： Peter Smeys ,  Peter Johnson ,  Gokhan Percin

    发明人： Peter Smeys ,  Peter Johnson ,  Gokhan Percin

    IPC分类号： H01L29/72

    CPC分类号： B06B1/0292 ,  H01L27/0688

    摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide features. For a particular embodiment, the SOI wafer comprises a single crystal epitaxial layer, a buried oxide layer and a silicon layer, and the single crystal epitaxial layer is bonded to the planarized oxide features, after which the silicon layer and the buried oxide layer of the SOI wafer are removed, leaving the single crystal epitaxial layer bonded to the oxide layer.

    摘要翻译： 提供一种用于形成电容微加工超声换能器（CMUT）的方法，其包括在硅晶片中的CMUT控制芯片外部形成氧化物特征。 氧化物的特征被平坦化。 绝缘体上硅（SOI）晶片与平坦化的氧化物特征结合。 对于特定实施例，SOI晶片包括单晶外延层，掩埋氧化物层和硅层，并且单晶外延层结合到平坦化的氧化物特征，之后硅层和掩埋氧化物层 去除SOI晶片，留下单晶外延层与氧化物层结合。

    Methods of forming inductors on integrated circuits
    4.
    发明授权
    Methods of forming inductors on integrated circuits 有权
    在集成电路上形成电感器的方法

    公开(公告)号：US08042260B2

    公开(公告)日：2011-10-25

    申请号：US12250385

    申请日：2008-10-13

    申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

    发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

    IPC分类号： H01F7/06

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

    摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.

    摘要翻译： 所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。 在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。 第一组间隔开的金属芯元件形成在衬底上。 然后在芯元件的侧表面上形成隔离侧壁。 之后，在衬底上形成第二组金属芯元件。 第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。 具体实施例涉及其他处理操作，例如不同类型的金属的选择性电镀以形成核心元件和/或沉积和蚀刻离开隔离层以在核心元件上形成隔离侧壁。

    CMOS COMPATIBLE INTEGRATED HIGH DENSITY CAPACITOR STRUCTURE AND PROCESS SEQUENCE
    6.
    发明申请
    CMOS COMPATIBLE INTEGRATED HIGH DENSITY CAPACITOR STRUCTURE AND PROCESS SEQUENCE 审中-公开
    CMOS兼容一体化高密度电容器结构和工艺顺序

    公开(公告)号：US20100079929A1

    公开(公告)日：2010-04-01

    申请号：US12243123

    申请日：2008-10-01

    申请人： Peter Smeys ,  Peter Johnson

    发明人： Peter Smeys ,  Peter Johnson

    IPC分类号： H01G9/07 ,  H01G9/00

    CPC分类号： H01G9/15 ,  H01G9/0032 ,  H01L21/02183 ,  H01L21/02258 ,  H01L21/31687 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

    摘要： Integrated circuits structures and process sequences are provided for forming CMOS compatible high-density capacitors. The anodization of tantalum to tantalum oxide in the formation of the inter-plate capacitor dielectric results in very high dielectric constants since the defects usually found in the inter-plate dielectric are eliminated in the volume expansion that occurs during the oxidation of the tantalum material. This permits the fabrication of larger capacitors that can be incorporated into standard CMOS process flows.

    摘要翻译： 集成电路结构和工艺顺序被提供用于形成CMOS兼容的高密度电容器。 在形成板间电容器电介质中，钽到氧化钽的阳极氧化导致非常高的介电常数，因为在钽材料的氧化期间发生的体积膨胀中消除了在板间电介质中通常发现的缺陷。 这允许制造可并入标准CMOS工艺流程的较大电容器。

    Method of fabricating an inductor structure
    9.
    发明授权
    Method of fabricating an inductor structure 有权
    制造电感器结构的方法

    公开(公告)号：US08205324B2

    公开(公告)日：2012-06-26

    申请号：US12275599

    申请日：2008-11-21

    申请人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

    发明人： Peter Smeys ,  Peter Johnson ,  Andrei Papou

    IPC分类号： H01F3/00 ,  H01F41/02

    CPC分类号： H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01L23/5227 ,  H01L2924/0002 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49144 ,  H01L2924/00

    摘要： A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.

    摘要翻译： 利用镶嵌工艺来制造集成电路电感器结构的分段磁芯元件。 磁芯从与保持永久介电模具的种子层电镀，导致侧壁镀层限定易磁轴。 硬轴平行于芯的纵轴延伸，并且电感线圈与芯的纵向轴线正交。 因此，由电感线圈产生的磁场与硬磁轴平行和自对准。 通过在平行于容易轴的施加磁场中电镀来增强易轴。