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    LOW PROFILE PACKAGE AND METHOD
    1.
    发明申请
    LOW PROFILE PACKAGE AND METHOD 审中-公开
    低配置文件包和方法

    公开(公告)号：US20120326300A1

    公开(公告)日：2012-12-27

    申请号：US13168701

    申请日：2011-06-24

    申请人： Tao FENG ,  Will K. WONG ,  Ashok S. PRABHU ,  Hau T. NGUYEN ,  Anindya PODDAR

    发明人： Tao FENG ,  Will K. WONG ,  Ashok S. PRABHU ,  Hau T. NGUYEN ,  Anindya PODDAR

    IPC分类号： H01L23/498 ,  H01L21/50

    CPC分类号： H01L23/5389 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

    摘要： In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

    摘要翻译： 在方法方面，多个IC连接到结构上支持的载体（例如晶片）上的布线。 骰子被封装，然后骰子和密封剂层都与载体一起变薄。 在第一密封剂层上形成第二布线层，并且提供导电通孔以根据需要电耦合第一和第二布线层。 提供外部I / O触点（例如焊料凸块）以便于将第二路由层（或堆叠封装中的后续路由层）电连接到外部设备。 然后以使至少部分地将外部I / O触点嵌入其中的方式在第一密封剂层和第二路由层上形成接触密封剂层。 在形成接触密封剂层之后，载体本身可能被显着地变薄并被分割以提供许多非常薄的包装。 所描述的方法也可以用于形成堆叠的多芯片封装。

    Spacer with passive components for use in multi-chip modules
    6.
    发明授权
    Spacer with passive components for use in multi-chip modules 有权
    带无源元件的隔板用于多芯片模块

    公开(公告)号：US06933597B1

    公开(公告)日：2005-08-23

    申请号：US10192173

    申请日：2002-07-09

    申请人： Anindya Poddar ,  Ashok S. Prabhu

    发明人： Anindya Poddar ,  Ashok S. Prabhu

    IPC分类号： H01L23/02 ,  H01L23/552 ,  H01L25/065

    CPC分类号： H01L25/0657 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A method for providing passive circuit functions in a multi-chip module and the multi-chip modules that result from incorporating these function is disclosed. Passive components such as resistors, capacitors and inductors are fabricated on or within a non-conductive spacer. The spacer is then placed between two active semiconductor dies and coupled electrically to either one or both of the dies. In this manner, area of the active dies that would normally have to be used for such passive components is freed for other uses and the spacer, which was already required in multi-chip modules, is endowed with extra functionality. In another embodiment, one or both surfaces of the spacer are coated with a conductive metal and the passive components are located within the spacer. In this embodiment, the spacer provides electromagnetic interference protection between the active dies.

    摘要翻译： 公开了一种在多芯片模块中提供无源电路功能的方法以及由这些功能引入的多芯片模块。 诸如电阻器，电容器和电感器的无源部件制造在非导电间隔件上或内部。 然后将间隔物放置在两个有源半导体管芯之间，并且电连接到裸片之一或两者。 以这种方式，通常必须用于这种无源部件的有源管芯的面积被释放用于其他用途，并且已经在多芯片模块中已经需要的间隔件具有额外的功能。 在另一个实施例中，间隔物的一个或两个表面涂覆有导电金属，并且无源部件位于间隔物内。 在该实施例中，间隔件在活动管芯之间提供电磁干扰保护。