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公开(公告)号：US4974147A
公开(公告)日：1990-11-27
申请号：US288639
申请日：1988-12-21
IPC分类号： G06F13/362 , G06F11/14 , G06F11/22 , G06F11/273 , G06F11/36 , G06F13/00
CPC分类号： G06F11/3648 , G06F11/14 , G06F11/22 , G06F11/2736
摘要： An apparatus for suspending processor operation in response to an error indication wherein the processor is cycled to a known state prior to the stopping of the system clock to enable the system to be interrogated in order to determine the cause of the error indication.
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2.发明授权Least recently used arbiter with programmable high priority mode and performance monitor 失效最近使用的可编程高优先级模式和性能监视器的仲裁器
公开(公告)号：US4953081A
公开(公告)日：1990-08-28
申请号：US288797
申请日：1988-12-21
IPC分类号： G06F13/362 , G06F13/364
CPC分类号： G06F13/364
摘要： In a data bus system which links a plurality of users, user access to the bus is provided by an arbiter which responds to a plurality of user requests for bus access by employing an adjustable priority scheme for granting access. When a user has access to the bus, the arbiter updates user priority by assigning the lowest priority to the current user and upwardly adjusting the priorities of all currently-requesting users.
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公开(公告)号：US5210828A
公开(公告)日：1993-05-11
申请号：US504764
申请日：1990-04-04
申请人： Timothy V. Bolan , Josephine A. Boston , George A. Fax , Donald J. Hanrahan , Bernhard Laubli , David A. Ring , Alfred T. Rundle , David J. Shippy
发明人： Timothy V. Bolan , Josephine A. Boston , George A. Fax , Donald J. Hanrahan , Bernhard Laubli , David A. Ring , Alfred T. Rundle , David J. Shippy
IPC分类号： G06F15/167
CPC分类号： G06F15/167
摘要： A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner. The processor interrupt circuitry facilitates the interprocessor communications process by handling interprocessor interrupts.
摘要翻译： 多个处理器连接到本发明的多处理系统中的处理器间通信设施。 处理器间通信设施具有仲裁电路，邮箱电路和处理器中断电路。 本发明的处理器间通信设施是集中式的，不需要使用主存储器。 这使得处理器能够以快速和有效的方式相互通信。 仲裁电路防止多个处理器同时访问处理器间通信设施，并根据命令解码从处理器发送的命令并将它们路由到处理器中断电路或邮箱电路。 本发明的邮箱电路从发送处理器接收消息，并以安全和可靠的方式将它们提供给预期的接收处理器。 处理器中断电路通过处理处理器间中断来促进处理器之间的通信过程。
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公开(公告)号：US07496776B2
公开(公告)日：2009-02-24
申请号：US10645024
申请日：2003-08-21
IPC分类号： G06F1/32
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。
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5.发明授权Data processing system parallel data bus having a single oscillator clocking apparatus 失效具有单个振荡器计时装置的数据处理系统并行数据总线
公开(公告)号：US4943984A
公开(公告)日：1990-07-24
申请号：US211032
申请日：1988-06-24
CPC分类号： G06F13/4217
摘要： A synchronous parallel data bus particularly adapted for use in a data processing system where it is necessary to transfer data over long distances. The physical connection between communicating units includes a plurality of wires adapted to carry the parallel data signal and a wire which carries a clock signal to the remote unit. When data is transmitted from the remote unit to the base unit, the clock signal which originated at the base unit and was transmitted to the remote unit is "turned around" and transmitted back to the base unit for use in receiving the data from the remote unit.
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公开(公告)号：US06957305B2
公开(公告)日：2005-10-18
申请号：US10232248
申请日：2002-08-29
申请人： David Scott Ray , David J. Shippy
发明人： David Scott Ray , David J. Shippy
CPC分类号： G06F12/0859 , G06F9/30047 , G06F12/0862 , G06F12/0897
摘要： This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level of the cache hierarchy to prefetch data into. A first asynchronous form of a DCBT instruction is issued to prefetch a stream of data into a L2 cache. A second synchronous form of a DCBT instruction is used to prefetch data from the L2 cache to the CRB in the main CPU, which will bypass the L1 data cache and forward data directly to the register file. This CRB has a dual usage and is used to hold both normal cache reloads as well as the aforementioned prefetched cache lines.
摘要翻译： 本发明提供了一种双重使用高速缓存重载缓冲器（CRB），用于保存需求负载以及预取负载。 数据高速缓存块触摸（DCBT）指令的新形式指定要将数据预取到哪个级别的缓存层次结构。 颁发DCBT指令的第一种异步形式，以将数据流预取到L 2高速缓存中。 DCBT指令的第二种同步形式用于将数据从L 2缓存预取到主CPU中的CRB，这将绕过L 1数据高速缓存并将数据直接转发到寄存器文件。 该CRB具有双重用途，用于保存正常缓存重新加载以及上述预取缓存行。
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7.发明授权Method and system for high performance dynamic and user programmable cache arbitration 失效高性能动态和用户可编程高速缓存仲裁的方法和系统
公开(公告)号：US5822758A
公开(公告)日：1998-10-13
申请号：US709793
申请日：1996-09-09
CPC分类号： G06F12/0897 , G06F13/18
摘要： A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information. In the second aspect, first logic coupled to the storage unit determines the priority of each of the plurality of events in response to the first signal and outputs a second signal indicating the priority of each event. Second logic coupled to the first logic grants access to the cache in response to the second signal.
摘要翻译： 公开了一种用于改善可能需要访问高速缓存的多个事件的仲裁的系统和方法。 在第一方面，该方法和系统提供动态仲裁。 第一方面包括用于确定多个事件中的至少一个是否需要访问高速缓冲存储器并且响应于此来输出至少一个信号的第一逻辑。 耦合到第一逻辑的第二逻辑响应于至少一个信号确定多个事件中的每一个的优先级，并且输出指定每个事件的优先级的第二信号。 耦合到第二逻辑的第三逻辑响应于第二信号而允许对高速缓存的访问。 该方法和系统的第二方面提供用户可编程仲裁。 第二方面包括存储单元，其允许用户输入指示多个事件中的至少一个的优先级的信息，并且响应于该信息输出第一信号。 在第二方面，耦合到存储单元的第一逻辑响应于第一信号确定多个事件中的每一个的优先级，并且输出指示每个事件的优先级的第二信号。 耦合到第一逻辑的第二逻辑响应于第二信号而允许对高速缓存的访问。
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公开(公告)号：US08051315B2
公开(公告)日：2011-11-01
申请号：US12269997
申请日：2008-11-13
IPC分类号： G06F1/32
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。
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9.发明授权Method and apparatus for coherent memory structure of heterogeneous processor systems 失效异构处理器系统的相干存储器结构的方法和装置公开(公告)号：US07093080B2
公开(公告)日：2006-08-15
申请号：US10682386
申请日：2003-10-09
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0835
摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
摘要翻译： 公开了与非均匀处理单元结合操作的一致的缓存系统。 一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。 需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。 每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。
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公开(公告)号：US20090070609A1
公开(公告)日：2009-03-12
申请号：US12269997
申请日：2008-11-13
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。
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