公开(公告)号：US09875044B2

公开(公告)日：2018-01-23

申请号：US14800783

申请日：2015-07-16

申请人： Dong Hwan Lee ,  Jun Jin Kong ,  Chang Kyu Seol ,  Hong Rak Son

发明人： Dong Hwan Lee ,  Jun Jin Kong ,  Chang Kyu Seol ,  Hong Rak Son

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F17/30 ,  G06F12/02 ,  G06F21/79 ,  G11C16/04

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/068 ,  G06F12/0246 ,  G06F17/3033 ,  G06F17/30867 ,  G06F21/79 ,  G11C16/0466

摘要： A method is provided for operating a data storage device capable of compensating for an initial threshold voltage shift of multiple memory cells. The method includes generating a first compression value for a first write address corresponding to a first write request input during a first time interval among different time intervals, and storing the first compression value in a first table among multiple tables.

公开(公告)号：US10229749B2

公开(公告)日：2019-03-12

申请号：US15475670

申请日：2017-03-31

申请人： Eun Chu Oh ,  Pilsang Yoon ,  Jun Jin Kong ,  Hong Rak Son ,  Dongsup Jin

发明人： Eun Chu Oh ,  Pilsang Yoon ,  Jun Jin Kong ,  Hong Rak Son ,  Dongsup Jin

IPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

摘要： A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.

公开(公告)号：US09864544B2

公开(公告)日：2018-01-09

申请号：US15001275

申请日：2016-01-20

申请人： Eun Chu Oh ,  Hong Rak Son ,  Jun Jin Kong ,  Seong Hyeog Choi

发明人： Eun Chu Oh ,  Hong Rak Son ,  Jun Jin Kong ,  Seong Hyeog Choi

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

CPC分类号： G06F3/0652 ,  G06F3/0614 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

摘要： A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.

公开(公告)号：US09158500B2

公开(公告)日：2015-10-13

申请号：US13537297

申请日：2012-06-29

申请人： Ki Jun Lee ,  Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim ,  Hong Rak Son ,  Jung Soo Chung ,  Seong Hyeong Choi

发明人： Ki Jun Lee ,  Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim ,  Hong Rak Son ,  Jung Soo Chung ,  Seong Hyeong Choi

IPC分类号： G06F7/58

CPC分类号： G06F7/584 ,  G06F2207/583

摘要： A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.

摘要翻译： 一种数据处理装置，包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器。 转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

公开(公告)号：US08711618B2

公开(公告)日：2014-04-29

申请号：US13190913

申请日：2011-07-26

申请人： Seong Hyeog Choi ,  Hong Rak Son ,  Jun Jin Kong ,  Yong June Kim

发明人： Seong Hyeog Choi ,  Hong Rak Son ,  Jun Jin Kong ,  Yong June Kim

IPC分类号： G11C7/10

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10

摘要： A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.

摘要翻译： 一种对包含在备用区域中的多级单元进行编程的方法，所述方法包括在第一多级单元中编程第一页数据和至少一个第一虚拟数据; 以及在第二多级单元中编程第二页数据和至少一个第二伪数据。

公开(公告)号：US20100251077A1

公开(公告)日：2010-09-30

申请号：US12729285

申请日：2010-03-23

申请人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

发明人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

IPC分类号： G06F12/02 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048

摘要： A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.

摘要翻译： 存储装置包括控制器单元和存储单元阵列。 控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。 存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。 第一存储器具有与第二存储器不同的存储单元结构。

公开(公告)号：US08799593B2

公开(公告)日：2014-08-05

申请号：US13237350

申请日：2011-09-20

申请人： Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

发明人： Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

IPC分类号： G06F13/28 ,  G06F12/02

CPC分类号： G06F12/0246

摘要： Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.

摘要翻译： 公开了一种闪速存储器件，其包括被配置为存储数据的存储器单元阵列，被配置为生成随机序列的随机器，以使用与要在存储器单元阵列中编程的数据相关联的存储器参数中的至少一个来交织随机序列， 以及控制逻辑电路，被配置为将所述存储器参数提供给所述随机发生器并且控制所述随机发生器。

公开(公告)号：US08706953B2

公开(公告)日：2014-04-22

申请号：US13096036

申请日：2011-04-28

申请人： Kyoung Lae Cho ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jaehong Kim ,  Hong Rak Son

发明人： Kyoung Lae Cho ,  Kwang Ho Kim ,  Jun Jin Kong ,  Jaehong Kim ,  Hong Rak Son

IPC分类号： G06F12/02

CPC分类号： H03M7/30

摘要： A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.

摘要翻译： 一种在数据存储装置的存储介质中存储数据的方法包括将输入数据存储在存储介质中，并从存储介质读取输入数据，并在数据存储装置的后台操作期间压缩读取的数据。

公开(公告)号：US20120166708A1

公开(公告)日：2012-06-28

申请号：US13237350

申请日：2011-09-20

申请人： Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

发明人： Jung Soo Chung ,  Yong June Kim ,  Hong Rak Son ,  Jun Jin Kong

IPC分类号： G06F12/02

CPC分类号： G06F12/0246

摘要： Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.

摘要翻译： 公开了一种闪速存储器件，其包括被配置为存储数据的存储器单元阵列，被配置为生成随机序列的随机器，以使用与要在存储器单元阵列中编程的数据相关联的存储器参数中的至少一个来交织随机序列， 以及控制逻辑电路，被配置为将所述存储器参数提供给所述随机发生器并且控制所述随机发生器。

公开(公告)号：US20110249496A1

公开(公告)日：2011-10-13

申请号：US13080809

申请日：2011-04-06

申请人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

发明人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.

摘要翻译： 提供了具有排列成行和列的存储单元的多位存储器件的编程方法。 程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器 第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。 第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。 在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差 。