公开(公告)号：US5923979A

公开(公告)日：1999-07-13

申请号：US922672

申请日：1997-09-03

申请人： Dorman C. Pitzer ,  Mike F. Chang ,  Hong Wang

发明人： Dorman C. Pitzer ,  Mike F. Chang ,  Hong Wang

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/402 ,  H01L29/7802

摘要： A planar DMOS power transistor (MOSFET) fabricated using only three masking steps, resulting in a significant reduction in fabrication cost. The resulting device is in terms of operations similar to prior art devices formed using more masking steps. Both the source and body regions are formed by implantations through the identical openings in the polysilicon/gate oxide layers into the substrate. After a subsequent glass layer is deposited and masked to expose openings, body contact regions are implanted into the source regions by overdosing the source region dopant concentration. The third masking step is the metal mask which also forms a termination structure.

摘要翻译： 仅使用三个掩模步骤制造的平面DMOS功率晶体管（MOSFET），导致制造成本的显着降低。 所得到的装置在类似于使用更多掩蔽步骤形成的现有技术装置的操作方面。 源区和体区都是通过将多晶硅/栅极氧化物层中相同的开口注入衬底而形成的。 在随后的玻璃层沉积并掩盖以暴露开口之后，通过过量掺杂源区域掺杂剂浓度将体接触区域注入源极区域。 第三掩蔽步骤是也形成端接结构的金属掩模。

公开(公告)号：US06277695B1

公开(公告)日：2001-08-21

申请号：US09293380

申请日：1999-04-16

申请人： Richard K. Williams ,  Sung-Shan Tai ,  Dorman C. Pitzer ,  Wayne B. Grabowski ,  Anthony Tsui ,  Mike F. Chang

发明人： Richard K. Williams ,  Sung-Shan Tai ,  Dorman C. Pitzer ,  Wayne B. Grabowski ,  Anthony Tsui ,  Mike F. Chang

IPC分类号： H01L21336

CPC分类号： H01L29/66719 ,  H01L29/66712

摘要： The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.

摘要翻译： 通过在MOSFET的栅极上制造侧壁间隔来形成垂直平面DMOSFET中的源极和体区的金属接触。 以这种方式将金属接触自对准到栅极，DMOSFET中的每个电池的横向尺寸可以显着减小，而不会有接触和栅极之间短路的风险，并且电池的堆积密度可以 增加。 以这种方式，可以实现装置的导通电阻的显着降低。

公开(公告)号：US5917216A

公开(公告)日：1999-06-29

申请号：US742326

申请日：1996-10-31

申请人： Brian H. Floyd ,  Dorman C. Pitzer ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Dorman C. Pitzer ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/7832

摘要： A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.

摘要翻译： 其导通状态的沟槽MOSFET导通电流通过积聚区域并且穿过沿着沟槽侧壁设置的反向耗尽势垒层。 通过相邻区域的栅极控制耗尽和从沟槽侧壁横向延伸到其中的耗尽阻挡层（具有在截面图中的“耳朵”并且与相邻区域相反的掺杂类型）的外观来实现阻塞。 漂移区。 该MOSFET具有优于现有技术的沟槽MOSFET的导通电阻率，并且在导通状态电阻方面具有良好的性能，同时具有优于现有技术的沟槽MOSFET的阻塞特性。 阻挡特性的改善由作为半导体掺杂区域的耗尽阻挡层提供。 在阻挡状态下，耗尽阻挡层完全或几乎完全耗尽，以防止寄生双极导电。 可以改变耗尽阻挡层的形状和程度，并且可能存在多于一个的耗尽阻挡层。

公开(公告)号：US4561168A

公开(公告)日：1985-12-31

申请号：US443765

申请日：1982-11-22

申请人： Dorman C. Pitzer ,  Edward J. Rice

发明人： Dorman C. Pitzer ,  Edward J. Rice

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/22

CPC分类号： H01L29/7802 ,  H01L29/7816 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42376 ,  Y10S148/082

摘要： An MOS transistor which is suitable for use in the VHF and UHF regions is fabricated in a semiconductor substrate, with the substrate serving as the drain. A body region is formed within the substrate. A layer of insulation is formed over the surface of the device, and a via is formed in the insulation layer to expose those portions of the body region where a groove is to be cut. A groove is then formed in such a manner as to cause the insulation layer to overhang the edge of the groove. A source region is then formed in the exposed portions of the body region beneath the insulation layer. A source electrode and gate electrode are then simultaneously formed, with the overhang of the insulation layer causing the source electrode and the gate electrode to be physically and electrically separated from each other. Well known processing techniques are then used, if desired, to form a second metalization layer to serve as electrical interconnects, and to provide a scratch protection layer.In accordance with another embodiment of this invention, a lateral MOS transistor is constructed where the drain region is formed in the substrate simultaneously with the formation of the source region.

摘要翻译： 适用于VHF和UHF区域的MOS晶体管制造在半导体衬底中，衬底用作漏极。 在衬底内形成体区。 在器件的表面上形成绝缘层，并且在绝缘层中形成通孔以露出要切割凹槽的身体区域的那些部分。 然后以使得绝缘层悬垂在凹槽的边缘上的方式形成凹槽。 然后在绝缘层下方的主体区域的暴露部分中形成源极区域。 然后同时形成源电极和栅电极，绝缘层的突出端使得源电极和栅极电极彼此物理上和电气上分离。 然后，如果需要，使用众所周知的处理技术来形成第二金属化层以用作电互连，并提供划痕保护层。 根据本发明的另一实施例，构造横向MOS晶体管，其中在形成源极区域的同时形成漏极区。

公开(公告)号：US5429964A

公开(公告)日：1995-07-04

申请号：US180265

申请日：1994-01-12

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L21/28167 ,  H01L21/02129 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

摘要翻译： 通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。 以这种方式，三维扩散效果被最小化，避免了穿孔。 讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集 。 栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。 还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。 该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

公开(公告)号：US5521409A

公开(公告)日：1996-05-28

申请号：US362674

申请日：1994-12-22

申请人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7811 ,  H01L21/28211 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/4238

摘要： A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. In this case, the second polycrystalline segment extends over a scribe-line section of the termination area so as to be scribed during a scribing operation.

摘要翻译： 功率MOSFET由具有主有源区和外围端接区的半导体主体（2000和2001）产生。 典型地具有基本均匀厚度的第一绝缘层（2002）位于活性和终止区域之上。 主要多晶部分（2003A / 2003B）位于主要在有效区域之上的第一绝缘层之上。 第一和第二外围多晶段（2003C1和2003C2）位于终止区域上方的第一绝缘层上。 栅电极（2016）与主多晶部分接触。 源电极（2015A / 2015B）接触有源区，端接区和第一多晶段。 可选的附加金属部分（2019）接触第二多晶段。 在这种情况下，第二多晶段在终止区域的划线部分上延伸，以便在划线操作期间划线。

公开(公告)号：US5304831A

公开(公告)日：1994-04-19

申请号：US881589

申请日：1992-05-12

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L27/01

CPC分类号： H01L21/28167 ,  H01L21/02129 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

摘要翻译： 通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。 以这种方式，三维扩散效果被最小化，避免了穿孔。 讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集 。 栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。 还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。 该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

公开(公告)号：US06534366B2

公开(公告)日：2003-03-18

申请号：US09816717

申请日：2001-03-21

申请人： Jacek Korec ,  Mohamed N. Darwish ,  Dorman C. Pitzer

发明人： Jacek Korec ,  Mohamed N. Darwish ,  Dorman C. Pitzer

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7811

摘要： A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

摘要翻译： 沟槽门控功率MOSFET在体区中包含高掺杂区域，其形成PN结二极管，漏极位于MOSFET单元的中心。 该二极管的雪崩击穿电压低于靠近沟槽壁的漏极 - 本体连接点的击穿电压。 因此，MOSFET在电池的中心分解，避免产生可能损坏栅极氧化物层的热载流子。 漏极 - 体结的位置处于沟槽底部以上的水平，从而避免任何深度扩散，从而增加电池宽度并降低电池堆积密度。 这种紧凑的结构通过限制在植入体区域之后暴露于器件的热预算来实现。 结果，体和其高掺杂区域不会显着扩散，并且来自高掺杂区域的掺杂剂不会进入器件的沟道区域，以增加其阈值电压。

公开(公告)号：US06348712B1

公开(公告)日：2002-02-19

申请号：US09428299

申请日：1999-10-27

申请人： Jacek Korec ,  Mohamed N. Darwish ,  Dorman C. Pitzer

发明人： Jacek Korec ,  Mohamed N. Darwish ,  Dorman C. Pitzer

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66734 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7811

摘要： A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

摘要翻译： 沟槽门控功率MOSFET在体区中包含高掺杂区域，其形成PN结二极管，漏极位于MOSFET单元的中心。 该二极管的雪崩击穿电压低于靠近沟槽壁的漏极 - 本体连接点的击穿电压。 因此，MOSFET在电池的中心分解，避免产生可能损坏栅极氧化物层的热载流子。 漏极 - 体结的位置处于沟槽底部以上的水平，从而避免任何深度扩散，从而增加电池宽度并降低电池堆积密度。 这种紧凑的结构通过限制在植入体区域之后暴露于器件的热预算来实现。 结果，体和其高掺杂区域不会显着扩散，并且来自高掺杂区域的掺杂剂不会进入器件的沟道区域，以增加其阈值电压。

公开(公告)号：US5404040A

公开(公告)日：1995-04-04

申请号：US96135

申请日：1993-07-22

申请人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan V. D. Linde

发明人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan V. D. Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68 ,  H01L21/265

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7811 ,  H01L21/28211 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/4238

摘要： A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. The MOSFET is typically created by a five-mask process. A defreckle etch is performed subsequent to metal deposition and patterning to define the two peripheral polycrystalline segments.

摘要翻译： 功率MOSFET由具有主有源区和外围端接区的半导体主体（2000和2001）产生。 基本上均匀厚度的第一绝缘层（2002）位于活性和终止区域之上。 主要多晶部分（2003A / 2003B）位于主要在有效区域之上的第一绝缘层之上。 第一和第二外围多晶段（2003C1和2003C2）位于终止区域上方的第一绝缘层上。 栅电极（2016）与主多晶部分接触。 源电极（2015A / 2015B）接触有源区，端接区和第一多晶段。 可选的附加金属部分（2019）接触第二多晶段。 MOSFET通常由五掩模工艺制成。 在金属沉积和图案化之后执行失真蚀刻以限定两个外围多晶段。