公开(公告)号：US5404040A

公开(公告)日：1995-04-04

申请号：US96135

申请日：1993-07-22

申请人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan V. D. Linde

发明人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan V. D. Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68 ,  H01L21/265

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7811 ,  H01L21/28211 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/4238

摘要： A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. The MOSFET is typically created by a five-mask process. A defreckle etch is performed subsequent to metal deposition and patterning to define the two peripheral polycrystalline segments.

摘要翻译： 功率MOSFET由具有主有源区和外围端接区的半导体主体（2000和2001）产生。 基本上均匀厚度的第一绝缘层（2002）位于活性和终止区域之上。 主要多晶部分（2003A / 2003B）位于主要在有效区域之上的第一绝缘层之上。 第一和第二外围多晶段（2003C1和2003C2）位于终止区域上方的第一绝缘层上。 栅电极（2016）与主多晶部分接触。 源电极（2015A / 2015B）接触有源区，端接区和第一多晶段。 可选的附加金属部分（2019）接触第二多晶段。 MOSFET通常由五掩模工艺制成。 在金属沉积和图案化之后执行失真蚀刻以限定两个外围多晶段。

公开(公告)号：US5429964A

公开(公告)日：1995-07-04

申请号：US180265

申请日：1994-01-12

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L21/28167 ,  H01L21/02129 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

摘要翻译： 通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。 以这种方式，三维扩散效果被最小化，避免了穿孔。 讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集 。 栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。 还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。 该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

公开(公告)号：US5521409A

公开(公告)日：1996-05-28

申请号：US362674

申请日：1994-12-22

申请人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7811 ,  H01L21/28211 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/4238

摘要： A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lies over the first insulating layer largely above the active area. First and second peripheral polycrystalline segments (2003C1 and 2003C2) lie over the first insulating layer above the termination area.A gate electrode (2016) contacts the main polycrystalline portion. A source electrode (2015A/2015B) contacts the active area, the termination area, and the first polycrystalline segment. An optional additional metal portion (2019) contacts the second polycrystalline segment. In this case, the second polycrystalline segment extends over a scribe-line section of the termination area so as to be scribed during a scribing operation.

摘要翻译： 功率MOSFET由具有主有源区和外围端接区的半导体主体（2000和2001）产生。 典型地具有基本均匀厚度的第一绝缘层（2002）位于活性和终止区域之上。 主要多晶部分（2003A / 2003B）位于主要在有效区域之上的第一绝缘层之上。 第一和第二外围多晶段（2003C1和2003C2）位于终止区域上方的第一绝缘层上。 栅电极（2016）与主多晶部分接触。 源电极（2015A / 2015B）接触有源区，端接区和第一多晶段。 可选的附加金属部分（2019）接触第二多晶段。 在这种情况下，第二多晶段在终止区域的划线部分上延伸，以便在划线操作期间划线。

公开(公告)号：US5304831A

公开(公告)日：1994-04-19

申请号：US881589

申请日：1992-05-12

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L27/01

CPC分类号： H01L21/28167 ,  H01L21/02129 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

摘要翻译： 通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。 以这种方式，三维扩散效果被最小化，避免了穿孔。 讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集 。 栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。 还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。 该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

公开(公告)号：US5559044A

公开(公告)日：1996-09-24

申请号：US323950

申请日：1994-10-17

申请人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

发明人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5583061A

公开(公告)日：1996-12-10

申请号：US464435

申请日：1995-06-05

申请人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

发明人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5618743A

公开(公告)日：1997-04-08

申请号：US463417

申请日：1995-06-05

申请人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

发明人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5541125A

公开(公告)日：1996-07-30

申请号：US463165

申请日：1995-06-05

申请人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

发明人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5451533A

公开(公告)日：1995-09-19

申请号：US318323

申请日：1994-10-05

申请人： Richard K. Williams ,  Kevin Jew ,  Jun W. Chen

发明人： Richard K. Williams ,  Kevin Jew ,  Jun W. Chen

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/78 ,  H01L29/1087 ,  Y10S148/126

摘要： A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.

摘要翻译： 包括不与衬底短路的源极和漏极的双向电流阻断横向功率MOSFET以及施加到源极和漏极的电压都高于保持体的电压（对于N沟道MOSFET ）或低于保持身体的电压（对于P沟道MOSFET）。 MOSFET的导通电阻通过降低外延区域的电导并且在源极和漏极区域之间的衬底的表面上设置薄的阈值调整层来提高。 可选的第二穿透防止植入物设置在基底表面上。

公开(公告)号：US5426328A

公开(公告)日：1995-06-20

申请号：US226419

申请日：1994-04-11

申请人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun W. Chen

发明人： Hamza Yilmaz ,  Richard K. Williams ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L29/861 ,  H01L29/70 ,  H01L27/102 ,  H01L29/73

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0638 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L2924/0002 ,  Y10S148/009 ,  Y10S148/085

摘要： A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种同时形成高质量互补双极晶体管，相对高电压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器或这些的任何期望组合的方法，全部在同一集成电路芯片上 。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。