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公开(公告)号：US10910945B2
公开(公告)日：2021-02-02
申请号：US16402905
申请日：2019-05-03
发明人： Mathieu Coustans , Lubomir Plavec , Mario Dellea
IPC分类号： H02M3/07
摘要： The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK1) and an output (S), a first capacitor (C1) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A1) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A2) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A3) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A4) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to the first source/drain terminal of the second and third transistors and a gate terminal coupled to the input. The gate terminal of the first transistor is coupled to the gate terminal of the second transistor.
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公开(公告)号：US09881692B2
公开(公告)日：2018-01-30
申请号：US14930785
申请日：2015-11-03
CPC分类号： G11C29/08 , G11C7/12 , G11C7/22 , G11C8/10 , G11C29/18 , G11C29/34 , G11C2029/1202 , G11C2029/2602
摘要： The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously.
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公开(公告)号：US20140347112A1
公开(公告)日：2014-11-27
申请号：US14365499
申请日：2012-12-13
发明人： Lubomir Plavec , Yves Theoduloz , Petr Drechsler
CPC分类号： H03K3/017 , H03K5/133 , H03K7/08 , H03K2005/00032 , H03L5/00
摘要： The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.
摘要翻译： 本发明涉及由电源电压供电的信号发生器电路，并且包括触发器装置，该触发器装置包括第一输入端，连接有连续输入信号的幅度被限定，第二输入端连接有定义占空比的时钟信号 和第三复位输入，并且输出其占空比是时钟信号的输出信号并且其幅度是输入信号的幅度的输出信号，其特征在于，所述电路还包括调节装置，用于将输出信号与一组 代表期望的占空比的信号，并传送连接到触发器装置的第三输入端的控制信号，以激活复位来修改输出信号的占空比。
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公开(公告)号：US09058862B2
公开(公告)日：2015-06-16
申请号：US14279486
申请日：2014-05-16
发明人： Lubomir Plavec , Filippo Marinelli
摘要： The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.
摘要翻译： 本发明涉及一种电压调节器和一种在复位模式和采样模式下操作电压调节器的方法。 电压调节器包括具有与第一电容器串联的第一电容器和第二电容器的电容性分压器，其中电容性分压器可连接到电压源的输出以激活采样模式，比较器具有输出连接到 所述比较器还具有连接到布置在所述第一电容器和所述第二电容器之间的采样节点的第一输入端，所述比较器具有连接到参考电压的第二输入，其中所述采样节点可连接到所述参考电压 激活复位模式的电压。
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公开(公告)号：US09281806B2
公开(公告)日：2016-03-08
申请号：US14365499
申请日：2012-12-13
发明人： Lubomir Plavec , Yves Theoduloz , Petr Drechsler
CPC分类号： H03K3/017 , H03K5/133 , H03K7/08 , H03K2005/00032 , H03L5/00
摘要： The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.
摘要翻译： 本发明涉及由电源电压供电的信号发生器电路，并且包括触发器装置，该触发器装置包括第一输入端，连接有连续输入信号的幅度被限定，第二输入端连接有定义占空比的时钟信号 和第三复位输入，并且输出其占空比是时钟信号的输出信号并且其幅度是输入信号的幅度的输出信号，其特征在于，所述电路还包括调节装置，用于将输出信号与一组 代表期望的占空比的信号，并传送连接到触发器装置的第三输入端的控制信号，以激活复位来修改输出信号的占空比。
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公开(公告)号：US09761283B2
公开(公告)日：2017-09-12
申请号：US15085392
申请日：2016-03-30
发明人： Lubomir Plavec , Filippo Marinelli
摘要： A memory circuit is provided, including at least one bit cell configured to store data and having a first terminal and a second terminal, one of the terminals being coupled to a bit-line; at least one current switch connected to the bit-line and connected to a current source and being configured to selectively provide at least a read current to the bit cell; and a sense amplifier having at least one input connected to a sensing node on the bit-line, wherein the sensing node is disposed between the bit cell and the at least one current switch.
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公开(公告)号：US09535109B2
公开(公告)日：2017-01-03
申请号：US14632511
申请日：2015-02-26
发明人： Lubomir Plavec , Zdenek Lukes
IPC分类号： G01R31/26 , H01L21/66 , H03K19/003 , H01L27/02
CPC分类号： G01R31/2621 , H01L22/34 , H01L27/0266 , H03K19/00315 , H03K19/00369
摘要： A fault detection assembly of an integrated circuit having a supply port, an input port and a ground port. The fault detection assembly includes a first diode connected with one end to the supply port and connected with the other end to the input port, a second diode connected with one end to the input port and connected with the other end to the ground port, at least a first fault detection transistor of MOS type. At least one of first and second diodes includes a first diode-connected MOS transistor whose gate is connected to the gate of the first fault detection transistor.
摘要翻译： 具有供电端口，输入端口和接地端口的集成电路的故障检测组件。 所述故障检测组件包括：第一二极管，其一端连接到所述供应端口并且与另一端连接到所述输入端口;第二二极管，其一端连接到所述输入端口，并且与另一端连接到所述接地端口; 至少是MOS型的第一故障检测晶体管。 第一和第二二极管中的至少一个包括第一二极管连接的MOS晶体管，其栅极连接到第一故障检测晶体管的栅极。
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