公开(公告)号：US06877910B2

公开(公告)日：2005-04-12

申请号：US10272002

申请日：2002-10-17

申请人： Eietsu Takahashi ,  Kazuo Nomura ,  Susumu Yamamoto ,  Hiroshi Matsumiya ,  Osamu Daikuhara ,  Shinichiro Kawaguchi ,  Noboru Shimizu ,  Hideo Miyazawa ,  Koji Watanabe ,  Hirohiko Tsugane ,  Naoki Ikemori

发明人： Eietsu Takahashi ,  Kazuo Nomura ,  Susumu Yamamoto ,  Hiroshi Matsumiya ,  Osamu Daikuhara ,  Shinichiro Kawaguchi ,  Noboru Shimizu ,  Hideo Miyazawa ,  Koji Watanabe ,  Hirohiko Tsugane ,  Naoki Ikemori

IPC分类号： G02B6/36 ,  B29C45/14 ,  B29C45/16 ,  B29C45/36 ,  B29K105/20 ,  B29L11/00 ,  B29L31/36 ,  G02B6/38

CPC分类号： G02B6/3835 ,  B29C45/16 ,  B29C45/1615 ,  B29C45/1676 ,  B29L2011/0075 ,  G02B6/3865 ,  Y10T16/39

摘要： A plastic ferrule including a centering section having a tubular body. The tubular body is provided with an outer-circumferential centering reference surface and a center axis of the centering reference surface. The centering section includes a resinous outer tube part having the outer-circumferential centering reference surface and provided, along the center axis, with a coated-fiber holding bore for securely accommodating a coated optical fiber and a fixing bore extending from the coated-fiber holding bore, the outer tube part forming a tubular wall with a generally uniform thickness as a whole. The centering section also includes an inner tube part fixed to the fixing bore of the outer tube part and provided along the center axis with an uncoated-fiber holding bore, communicating with the coated-fiber holding bore, for securely accommodating an uncoated optical fiber.

摘要翻译： 一种塑料套管，包括具有管状体的定心部分。 管体具有外圆周对中基准面和中心基准面的中心轴线。 定心部包括具有外圆周对中面的树脂外管部，沿着中心轴线设置有用于牢固地容纳被覆光纤的涂布纤维保持孔和从涂覆光纤保持件延伸的固定孔 孔，外管部分形成整体上具有大致均匀厚度的管状壁。 中心部分还包括固定到外管部分的固定孔的内管部分，并且沿着中心轴线设置有与涂覆纤维保持孔连通的未涂覆纤维保持孔，用于牢固地容纳未涂覆的光纤。

公开(公告)号：US08873298B2

公开(公告)日：2014-10-28

申请号：US13451843

申请日：2012-04-20

申请人： Yasuhiro Shiino ,  Eietsu Takahashi

发明人： Yasuhiro Shiino ,  Eietsu Takahashi

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5644

摘要： A nonvolatile semiconductor storage device according to an embodiment includes: a memory cell array including plural memory cells; and a control circuit that repeatedly performs a write loop including a program operation and a verify operation in data write performed to the memory cell, the verify operation including a preverify step to check whether a threshold voltage of the memory cell transitions to a preverify voltage, and a real verify step to check whether the threshold voltage of the memory cell transitions to the real verify voltage, the write loop including one or at least two verify operations corresponding to pieces of the data, the control circuit performing the write loop in which the preverify step of the verify operation corresponding to a first data is omitted after obtaining a first condition.

摘要翻译： 根据实施例的非易失性半导体存储装置包括：包括多个存储单元的存储单元阵列; 以及控制电路，其重复执行包括对所述存储单元执行的数据写入中的编程操作和验证操作的写入循环，所述验证操作包括预验证步骤，用于检查所述存储器单元的阈值电压是否转换到预验电压， 以及真实验证步骤，用于检查存储器单元的阈值电压是否转换到真实验证电压，写入循环包括与数据片段相对应的一个或至少两个验证操作，该控制电路执行写入循环，其中 在获得第一条件之后，省略对与第一数据相对应的验证操作的预验证步骤。

公开(公告)号：US08737134B2

公开(公告)日：2014-05-27

申请号：US13417719

申请日：2012-03-12

申请人： Yasuhiro Shiino ,  Eietsu Takahashi ,  Yuji Takeuchi

发明人： Yasuhiro Shiino ,  Eietsu Takahashi ,  Yuji Takeuchi

IPC分类号： G11C11/34

CPC分类号： G11C16/06 ,  G11C16/0483 ,  G11C16/344

摘要： A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.

摘要翻译： 根据实施例的非易失性半导体存储装置包括驱动电路。 将连接到与存储器串相邻的第一虚拟单元的虚设电路施加的虚拟电路的电压定义为第一虚拟线电压，施加到与第一虚拟单元相邻的与第一存储单元相连的选择线的电压被定义为 第一选择线电压和施加到连接到与第一存储器单元相邻的第二存储单元的选择线的电压被定义为第二选择线电压。 当在擦除操作中第二选择线电压低于第一虚拟线电压时，驱动电路控制电压，使得第一虚拟线电压和第二选择线电压之间的差小于第一虚拟线 电压和第一选择线电压。

公开(公告)号：US08385126B2

公开(公告)日：2013-02-26

申请号：US13246004

申请日：2011-09-27

申请人： Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

发明人： Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3427 ,  G11C16/349

摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

公开(公告)号：US08867277B2

公开(公告)日：2014-10-21

申请号：US13601233

申请日：2012-08-31

申请人： Tatsuo Izumi ,  Eietsu Takahashi

发明人： Tatsuo Izumi ,  Eietsu Takahashi

IPC分类号： G11C11/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30

CPC分类号： G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

摘要： A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times.

摘要翻译： 包括与选定字线相邻的字线的第一非选择字线被施加第一写通电压。 此外，作为除了第一未选择字线之外的未选择字线的第二非选择字线被施加小于编程电压的第二写入通过电压。 在写入操作中，控制电路通过执行具有第一电压上升幅度X倍的升压动作将第一写入通过电压提高到第一目标值，并且通过执行第二写入通过电压向第二目标值升高第二写入通过电压 具有第二电压上升宽度的升压操作Y次。 第一电压上升幅度大于第二电压上升幅度，X倍少于Y倍。

公开(公告)号：US08446777B2

公开(公告)日：2013-05-21

申请号：US13280618

申请日：2011-10-25

申请人： Koki Ueno ,  Eietsu Takahashi ,  Shigefumi Irieda ,  Yasuhiro Shiino ,  Manabu Sakaniwa

发明人： Koki Ueno ,  Eietsu Takahashi ,  Shigefumi Irieda ,  Yasuhiro Shiino ,  Manabu Sakaniwa

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/344

摘要： A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number

摘要翻译： 根据本发明的一个实施例的非易失性半导体存储器件包括存储单元阵列和控制单元。 控制单元被配置为控制擦除操作，擦除验证操作和升压操作的重复。 控制单元被配置为执行将存储单元从过擦除状态设置为第一阈值电压分布状态的软编程操作，当在一系列擦除操作中擦除电压应用的数量多于第一阈值电压分配状态时， 数字和小于第二个数字（第一个数字<第二个数字）。 当擦除电压应用的数量等于或小于第一数量或等于或大于第二数量时，控制单元被配置为不执行软编程操作。

公开(公告)号：US20130058171A1

公开(公告)日：2013-03-07

申请号：US13425121

申请日：2012-03-20

申请人： Yasuhiro SHIINO ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

发明人： Yasuhiro SHIINO ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3418

摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.

摘要翻译： 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。

公开(公告)号：US08149631B2

公开(公告)日：2012-04-03

申请号：US12796964

申请日：2010-06-09

申请人： Yasuhiro Shiino ,  Daisuke Kouno ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi

发明人： Yasuhiro Shiino ,  Daisuke Kouno ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi

IPC分类号： G11C11/34

CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/3445

摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.

摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。

公开(公告)号：US20120069672A1

公开(公告)日：2012-03-22

申请号：US13169414

申请日：2011-06-27

申请人： Yasuhiro SHIINO ,  Eietsu Takahashi ,  Yuji Takeuchi

发明人： Yasuhiro SHIINO ,  Eietsu Takahashi ,  Yuji Takeuchi

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3418

摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.

摘要翻译： 根据实施例的非易失性半导体存储器件包括存储单元阵列。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。 控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。 控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作 值小于第一升压值。

公开(公告)号：US4747667A

公开(公告)日：1988-05-31

申请号：US860483

申请日：1986-05-07

申请人： Akira Tanaka ,  Eietsu Takahashi ,  Masao Tanaka ,  Minoru Terashima ,  Toshito Hara

发明人： Akira Tanaka ,  Eietsu Takahashi ,  Masao Tanaka ,  Minoru Terashima ,  Toshito Hara

IPC分类号： G03G15/00 ,  G02B3/00 ,  G02B17/00 ,  G02B17/08 ,  G02B27/18 ,  G02B13/26 ,  G02B5/04

CPC分类号： G02B17/086 ,  G02B17/002 ,  G02B17/008 ,  G02B3/0068

摘要： A plastic lens array including the following members which are formed integrally as one block by a plastic material; a lens array body member; a plurality of object convex lenses into which the light from an object is made incident, the object convex lenses being arranged side by side in one row along one side of the lens array body member; a plurality of image convex lenses corresponding to the object convex lenses, and being arranged side by side in a row along an opposite side of the lens array body member; a plurality of image inverting portions corresponding to the object convex lenses, each of the image inverting portions having a pair of roof surfaces which are substantially normal to each other to invert the image of an object; a first reflecting surface arranged at the backs of the object convex lenses, for totally reflecting the incident light of an object through the object convex lenses with an angle exceeding a critical angle and for guiding the reflected light of the object to a roof surface in each pair of the roof surfaces; and a second reflecting surface arranged at the backs of the image convex lenses, for totally reflecting the inverted light of an object from the other roof surface in each pair of the roof surfaces with an angle exceeding the critical angle and for guiding the reflected light of an object to the image convex lenses.

摘要翻译： 一种塑料透镜阵列，包括由塑料材料一体形成的下列构件; 透镜阵列体部件; 使来自物体的光入射到其中的多个物体凸透镜，物镜凸透镜沿着透镜阵列本体构件的一侧并排布置成一列; 多个与物体凸透镜相对应的图像凸透镜，并且沿着透镜阵列本体构件的相对侧并排布置; 对应于物体凸透镜的多个图像反转部分，每个图像翻转部分具有大致相互垂直的一对顶表面，以反转物体的图像; 第一反射面，布置在物体凸透镜的后部，用于通过物体凸透镜以超过临界角的角度全反射物体的入射光，并将物体的反射光引导到每个 一对屋顶表面; 以及布置在图像凸透镜的后部的第二反射表面，用于以超过临界角的角度全面地反映来自每对屋顶表面中的另一屋顶表面的物体的倒置的光，并且用于引导 图像凸透镜的对象。