公开(公告)号：US07035750B2

公开(公告)日：2006-04-25

申请号：US10759912

申请日：2004-01-16

申请人： Elida Isabel de Obaldia ,  Chih-Ming Hung ,  Dirk Leipold ,  Oren Eliezer

发明人： Elida Isabel de Obaldia ,  Chih-Ming Hung ,  Dirk Leipold ,  Oren Eliezer

IPC分类号： G01R31/00

CPC分类号： H03K5/08 ,  H04B17/102 ,  H04B17/16 ,  H04B17/20

摘要： An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.

摘要翻译： 用于收发器功率放大器和振荡器频率的片上测试机制，用于集成RF收发器的发射器部分。 发射机功率放大器的RF输出被输入到具有可配置阈值的内置专用模拟比较器。 阈值被调整到在比较器输出处开始发生交叉的预定电平。 仅当功率放大器输出高于最小可配置电平时，比较器才会输出脉冲。 比较器输出被输入到分频器，其频率输出由低成本外部测试仪测试以确定实际RF频率，从而确认产生正确的振荡器频率，并且功率放大器输出端的信号幅度足够 可以超过可配置的阈值电平，从而确定输出功率与其规定的规格的一致性。

公开(公告)号：US07254755B2

公开(公告)日：2007-08-07

申请号：US10759911

申请日：2004-01-16

申请人： Elida Isabel de Obaldia ,  Dirk Leipold ,  Oren Eliezer ,  Ran Katz ,  Bogdan Staszewski

发明人： Elida Isabel de Obaldia ,  Dirk Leipold ,  Oren Eliezer ,  Ran Katz ,  Bogdan Staszewski

IPC分类号： H04B17/00

CPC分类号： H04B17/0085 ,  G01R31/2822 ,  H04B17/29 ,  H04L1/24

摘要： An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.

摘要翻译： 用于集成RF发射机的片上接收机灵敏度测试机构，其中发射机和接收机共享相同的振荡器。 该机构避免了使用具有内置调制能力的昂贵的RF信号发生器测试设备的需要，并且允许使用非常低成本的外部RF测试设备。 本发明利用已经存在于收发器中的电路，即调制电路和本地振荡器来执行灵敏度测试。 片上LO用于产生调制测试信号，否则将需要由具有调制能力的昂贵的外部RF测试设备提供。 调制的LO信号与外部产生的未调制的CW RF信号混合以在IF处产生调制信号，随后由接收机链的其余部分处理。 恢复的数据位使用片上BER计或计数器进行比较，产生BER读数。 BER读取在外部使用或由片上处理器或控制器用于建立芯片的通过/失败指示。

公开(公告)号：US07958408B2

公开(公告)日：2011-06-07

申请号：US11835274

申请日：2007-08-07

申请人： Elida Isabel de Obaldia ,  Dirk Leipold ,  Oren Eliezer ,  Ran Katz ,  Bogdan Staszewski

发明人： Elida Isabel de Obaldia ,  Dirk Leipold ,  Oren Eliezer ,  Ran Katz ,  Bogdan Staszewski

IPC分类号： H04B17/00

CPC分类号： H04B17/0085 ,  G01R31/2822 ,  H04B17/29 ,  H04L1/24

摘要： An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.

摘要翻译： 用于集成RF发射机的片上接收机灵敏度测试机构，其中发射机和接收机共享相同的振荡器。 该机构避免了使用具有内置调制能力的昂贵的RF信号发生器测试设备的需要，并且允许使用非常低成本的外部RF测试设备。 本发明利用已经存在于收发器中的电路，即调制电路和本地振荡器来执行灵敏度测试。 片上LO用于产生调制测试信号，否则将需要由具有调制能力的昂贵的外部RF测试设备提供。 调制的LO信号与外部产生的未调制的CW RF信号混合以在IF处产生调制信号，随后由接收器链的其余部分处理。 恢复的数据位使用片上BER计或计数器进行比较，产生BER读数。 BER读取在外部使用或由片上处理器或控制器用于建立芯片的通过/失败指示。

公开(公告)号：US07813462B2

公开(公告)日：2010-10-12

申请号：US11550878

申请日：2006-10-19

申请人： Elida Isabel de Obaldia ,  Robert B. Staszewski ,  Dirk Leipold

发明人： Elida Isabel de Obaldia ,  Robert B. Staszewski ,  Dirk Leipold

IPC分类号： H03D3/24

CPC分类号： H04L27/361 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/1806

摘要： A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.

摘要翻译： 一种用于定义数字RF处理器（DRP）中的处理变化的新颖方法和装置。 本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。 该方法和装置提供对电路中制造工艺变化的直接测量，而不需要使用已经存在于芯片中的时间 - 数字转换器（TDC）电路的任何额外的测试设备。 TDC电路依赖于逆变器链中的时间延迟，使用缓慢的FREF时钟采样高速CKV时钟。 逆时间的计算提供了每个模具中制造工艺变化的直接相关性。

公开(公告)号：US20060033582A1

公开(公告)日：2006-02-16

申请号：US11149859

申请日：2005-06-10

申请人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

发明人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

IPC分类号： H03L7/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L2207/50

摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

摘要翻译： 一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。 增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。 然后将梯度缩放并添加到DCO增益乘数的当前值。

公开(公告)号：US07405685B2

公开(公告)日：2008-07-29

申请号：US11178993

申请日：2005-07-11

申请人： Sameh S. Rezeq ,  Dirk Leipold ,  Robert B. Staszewski ,  Chih-Ming Hung

发明人： Sameh S. Rezeq ,  Dirk Leipold ,  Robert B. Staszewski ,  Chih-Ming Hung

IPC分类号： H03M3/00

CPC分类号： H03F1/0205 ,  H03F1/3241 ,  H03F2200/331 ,  H03F2200/375 ,  H03M3/356 ,  H03M3/50 ,  H03M7/3026 ,  H03M7/3037 ,  H04L27/368

摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.

摘要翻译： 一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。 来自Σ-Δ调制器的正输出的处理方式与负输出不同。 与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。 时钟的非反相版本与正输出一起使用，反向时钟与负输出一起使用。 使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。 结果是具有零偏移的偏移补偿RF输出信号。

公开(公告)号：US06734741B2

公开(公告)日：2004-05-11

申请号：US10006607

申请日：2001-11-30

申请人： Robert B. Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Chih-Ming Hung

发明人： Robert B. Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Chih-Ming Hung

IPC分类号： H03L700

CPC分类号： H03C3/0975 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03K19/0016 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/50 ,  H04L7/0029

摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.

公开(公告)号：US20080042872A1

公开(公告)日：2008-02-21

申请号：US11835274

申请日：2007-08-07

申请人： Elida de Obaldia ,  Dirk Leipold ,  Oren Eliezer ,  Ran Katz ,  Bogdan Staszewski

发明人： Elida de Obaldia ,  Dirk Leipold ,  Oren Eliezer ,  Ran Katz ,  Bogdan Staszewski

IPC分类号： G08C15/00

CPC分类号： H04B17/0085 ,  G01R31/2822 ,  H04B17/29 ,  H04L1/24

摘要： An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. Tile on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.

摘要翻译： 用于集成RF发射机的片上接收机灵敏度测试机构，其中发射机和接收机共享相同的振荡器。 该机构避免了使用具有内置调制能力的昂贵的RF信号发生器测试设备的需要，并且允许使用非常低成本的外部RF测试设备。 本发明利用已经存在于收发器中的电路，即调制电路和本地振荡器来执行灵敏度测试。 瓦片片上LO用于产生调制测试信号，否则将需要由具有调制能力的昂贵的外部RF测试设备提供。 调制的LO信号与外部产生的未调制的CW RF信号混合以在IF处产生调制信号，随后由接收机链的其余部分处理。 恢复的数据位使用片上BER计或计数器进行比较，产生BER读数。 BER读数在外部使用或由片上处理器或控制器用于建立芯片的通过/失败指示。

公开(公告)号：US20070008199A1

公开(公告)日：2007-01-11

申请号：US11178993

申请日：2005-07-11

申请人： Sameh Rezeq ,  Dirk Leipold ,  Robert Staszewski ,  Chih-Ming Hung

发明人： Sameh Rezeq ,  Dirk Leipold ,  Robert Staszewski ,  Chih-Ming Hung

IPC分类号： H03M1/06

CPC分类号： H03F1/0205 ,  H03F1/3241 ,  H03F2200/331 ,  H03F2200/375 ,  H03M3/356 ,  H03M3/50 ,  H03M7/3026 ,  H03M7/3037 ,  H04L27/368

摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.

摘要翻译： 一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。 来自Σ-Δ调制器的正输出的处理方式与负输出不同。 与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。 时钟的非反相版本与正输出一起使用，反时限与负输出一起使用。 使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。 结果是具有零偏移的偏移补偿RF输出信号。

公开(公告)号：US07023272B2

公开(公告)日：2006-04-04

申请号：US10827577

申请日：2004-04-19

申请人： Chih-Ming Hung ,  Dirk Leipold ,  Yo-Chuol Ho

发明人： Chih-Ming Hung ,  Dirk Leipold ,  Yo-Chuol Ho

IPC分类号： H03F3/68

CPC分类号： H03F3/45179 ,  H03F1/223 ,  H03F1/565 ,  H03F3/193 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/492 ,  H03F2203/45394 ,  H03F2203/7209

摘要： A low noise amplifier (LNA) operates over multiple frequency bands while occupying less silicon area than known LNA implementations. The LNA includes output matching that can be tuned by an adjustable inductor together with a tunable capacitor bank.

摘要翻译： 低噪声放大器（LNA）在多个频带上工作，而占用比已知LNA实现更少的硅面积。 LNA包括可调谐电感器和可调电容器组一起调谐的输出匹配。