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公开(公告)号：US20120223372A1
公开(公告)日：2012-09-06
申请号：US13039678
申请日：2011-03-03
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/32053 , H01L21/28518 , H01L29/66477 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.
摘要翻译： 本发明的一个方面包括用于形成具有两步硅化物形成的半导体器件的方法。 首先，在源极/漏极区域和相邻延伸区域的一部分上形成硅化物混合层。 可以更换任何用于完成此操作的垫片。 电介质材料覆盖源极/漏极区域上的硅化物混合层。 用于通孔的接触开口蚀刻到电介质材料中。 第二硅化物接触形成在硅化物混合层上，或者可以形成在源/漏区内，只要第二硅化物接触仍然接触硅化物混合层。
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公开(公告)号：US08652914B2
公开(公告)日：2014-02-18
申请号：US13039678
申请日：2011-03-03
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/32053 , H01L21/28518 , H01L29/66477 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.
摘要翻译： 本发明的一个方面包括用于形成具有两步硅化物形成的半导体器件的方法。 首先，在源极/漏极区域和相邻延伸区域的一部分上形成硅化物混合层。 可以更换任何用于完成此操作的垫片。 电介质材料覆盖源极/漏极区域上的硅化物混合层。 用于通孔的接触开口蚀刻到电介质材料中。 第二硅化物接触形成在硅化物混合层上，或者可以形成在源/漏区内，只要第二硅化物接触仍然接触硅化物混合层。
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3.发明申请METHOD OF FORMING SILICIDE CONTACTS OF DIFFERENT SHAPES SELECTIVELY ON REGIONS OF A SEMICONDUCTOR DEVICE 有权在半导体器件领域中选择形成不同形状的硅氧烷接触的方法公开(公告)号：US20120273798A1
公开(公告)日：2012-11-01
申请号：US13097459
申请日：2011-04-29
申请人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
发明人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
IPC分类号： H01L29/772
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0847 , H01L29/66636 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.
摘要翻译： 提供了一种用于制造用于半导体器件的硅化物触点的结构和方法。 具体地，该结构和方法涉及利用化学气相沉积（CVD）和退火以在半导体场效应晶体管（FET）（例如源极和漏极区域）的区域上选择性地形成不同形状的硅化物接触。 硅化物触点的形状是可以被操纵以降低接触电阻的关键因素。 因此，该结构和方法提供具有低接触电阻的不同形状的硅化物触点，其中硅化物触点还减轻漏电流以增强低功率应用中的FET的效用和性能。
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4.发明授权Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device 有权在半导体器件的区域上选择性地形成不同形状的硅化物触点的方法公开(公告)号：US08415250B2
公开(公告)日：2013-04-09
申请号：US13097459
申请日：2011-04-29
申请人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
发明人： Emre Alptekin , Dong-Ick Lee , Viraj Yashawant Sardesai , Cung Do Tran , Jian Yu , Reinaldo Ariel Vega , Rajasekhar Venigalla
IPC分类号： H01L29/417
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/76805 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0847 , H01L29/66636 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.
摘要翻译： 提供了一种用于制造用于半导体器件的硅化物触点的结构和方法。 具体地，该结构和方法涉及利用化学气相沉积（CVD）和退火以在半导体场效应晶体管（FET）（例如源极和漏极区域）的区域上选择性地形成不同形状的硅化物接触。 硅化物触点的形状是可以被操纵以降低接触电阻的关键因素。 因此，该结构和方法提供具有低接触电阻的不同形状的硅化物触点，其中硅化物触点还减轻漏电流以增强低功率应用中的FET的效用和性能。
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公开(公告)号：US20130273737A1
公开(公告)日：2013-10-17
申请号：US13448497
申请日：2012-04-17
IPC分类号： H01L21/02
CPC分类号： H01L21/02068 , H01L21/02063 , H01L21/28518 , H01L21/76814
摘要： Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.
摘要翻译： 本发明的实施例包括清洁器件结构的半导体衬底的方法和在器件结构的半导体衬底上形成硅化物层的方法。 实施例包括将衬底的顶部转换成氧化物层并去除氧化物层以暴露衬底的无污染物表面的步骤。
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公开(公告)号：US20130020705A1
公开(公告)日：2013-01-24
申请号：US13186519
申请日：2011-07-20
申请人： Emre Alptekin , Viraj Y. Sardesai , Cung D. Tran , Bin Yang
发明人： Emre Alptekin , Viraj Y. Sardesai , Cung D. Tran , Bin Yang
CPC分类号： H01L23/485 , H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/28518 , H01L21/76814 , H01L2924/0002 , H01L2924/00
摘要： Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.
摘要翻译： 方法通过在衬底内和/或衬底上形成多个器件的至少一部分形成集成电路结构，并且在邻近器件的衬底上的层间电介质层中图案化沟槽。 图案形成相对较窄的沟槽和较宽的沟槽。 然后，所述方法对沟槽进行补偿材料的成角度注入。 成角度的植入物的角度相对于在较窄沟槽的底部注入衬底的区域中的补偿材料的量，在较宽沟槽底部的衬底区域中植入更大浓度的补偿材料。 然后，该方法将金属材料沉积在沟槽内，并加热金属材料以从金属材料形成硅化物。
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公开(公告)号：US08298895B1
公开(公告)日：2012-10-30
申请号：US13285282
申请日：2011-10-31
申请人： Emre Alptekin
发明人： Emre Alptekin
IPC分类号： H01L21/336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/82385 , H01L29/0684 , H01L29/1041 , H01L29/66537
摘要： In a replacement metal gate process flow, sacrificial gates are exposed and removed subsequent to the formation of source and drain regions for various transistor devices. Sidewalls formed adjacent to the sacrificial gates remain. By using an angled implant such that, for a short-channel device, the remaining sidewalls shadow and protect the exposed short-channel region, a designer may adjust the threshold voltage on long-channel devices without affecting the threshold voltage of the short-channel device.
摘要翻译： 在替代的金属栅极工艺流程中，在形成用于各种晶体管器件的源极和漏极区域之后，牺牲栅极被暴露和去除。 与牺牲栅相邻形成的侧壁保留。 通过使用成角度的植入物，使得对于短通道器件，剩余的侧壁阴影并保护暴露的短沟道区域，设计者可以调整长沟道器件上的阈值电压而不影响短沟道的阈值电压 设备。
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公开(公告)号：US10103226B2
公开(公告)日：2018-10-16
申请号：US13459278
申请日：2012-04-30
申请人： Reinaldo A. Vega , Emre Alptekin , Hung H. Tran , Xiaobin Yuan
发明人： Reinaldo A. Vega , Emre Alptekin , Hung H. Tran , Xiaobin Yuan
IPC分类号： H01L21/336 , H01L29/06 , H01L29/66 , H01L29/739 , H01L29/78 , H01L21/28
摘要： A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.
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公开(公告)号：US20130334693A1
公开(公告)日：2013-12-19
申请号：US13525401
申请日：2012-06-18
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/02063 , H01L21/28525 , H01L21/76814 , H01L21/823814 , H01L23/485 , H01L29/665 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
摘要翻译： 一种用于形成硅化物接触的方法，所述方法包括使用气体簇注入技术沉积硅层，所述气体簇注入技术加速硅原子簇，使得它们穿过硅化物的顶表面上的表面氧化物; 将包括硅层的硅化物加热到约300℃至约950℃的温度，并在惰性气氛中保持约0.1毫秒至约600秒的温度，从而使来自硅层的硅部分地与剩余的硅化物部分地反应 形成在含硅衬底中; 以及从所述硅层形成凸起的硅化物，其中所述凸起的硅化物的厚度大于所述硅化物的厚度，并且所述硅化物在所述含硅衬底的顶表面上方突出。
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10.发明授权Method of manufacturing dummy gates of a different material as insulation between adjacent devices 有权制造不同材料的虚拟栅极作为相邻器件之间绝缘的方法公开(公告)号：US09059308B2
公开(公告)日：2015-06-16
申请号：US13564792
申请日：2012-08-02
IPC分类号： H01L21/8238 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/49
CPC分类号： H01L21/823481 , H01L21/823437 , H01L21/823828 , H01L27/088 , H01L29/49 , H01L29/66545
摘要： Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.
摘要翻译： 本发明的实施例包括由不同材料的虚拟栅极隔开的两个晶体管结构的半导体结构和用于形成所述结构的方法。 实施例包括在半导体衬底上形成牺牲栅极，在牺牲栅上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源/漏区，以及用绝缘材料代替第三牺牲栅。 替代第三牺牲栅极的绝缘材料可以用作虚拟栅极以电隔离附近的源极/漏极区域。 实施例还包括在半导体衬底上形成牺牲栅极，在牺牲栅极上形成间隔物，形成与由第三牺牲栅极隔开的两个牺牲栅极相邻的源极/漏极区域，并且在离开第三牺牲栅极的同时用金属栅极替换两个牺牲栅极 到位作为虚拟门。
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