公开(公告)号：US06967160B1

公开(公告)日：2005-11-22

申请号：US11042194

申请日：2005-01-26

申请人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

发明人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.

摘要翻译： 通过在下面的硅和硅化镍层之间形成扩散转换层来实现具有显着降低的界面粗糙度的硅化镍形成。 实施例包括将氮离子注入到衬底和栅电极中，沉积钛或钽的薄层，沉积镍层，然后加热以形成在下硅和硅化镍层之间的界面处含有氮的扩散调制层。

公开(公告)号：US06873051B1

公开(公告)日：2005-03-29

申请号：US10157807

申请日：2002-05-31

申请人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

发明人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.

摘要翻译： 通过在下面的硅和硅化镍层之间形成扩散转换层来实现具有显着降低的界面粗糙度的硅化镍形成。 实施例包括将氮离子注入到衬底和栅电极中，沉积钛或钽的薄层，沉积镍层，然后加热以形成在下硅和硅化镍层之间的界面处含有氮的扩散调制层。

公开(公告)号：US06689688B2

公开(公告)日：2004-02-10

申请号：US10180858

申请日：2002-06-25

申请人： Paul Raymond Besser ,  Simon S. Chan ,  David E. Brown ,  Eric Paton

发明人： Paul Raymond Besser ,  Simon S. Chan ,  David E. Brown ,  Eric Paton

IPC分类号： H01L2144

CPC分类号： H01L21/28518

摘要： A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide. The contacts may be part of a semiconductor device including a substrate, active region containing silicon, and silicide contacts disposed over the active region and capable of electrically coupling the active region to other regions such as metallization lines.

摘要翻译： 用于形成硅化物接触的方法包括在诸如源极，漏极和栅极区域的含硅有源器件区域上形成层。 该层包含能够形成一种或多种金属硅化物的金属和可溶于第一金属硅化物但不溶于第二金属硅化物的材料，或者比第二金属硅化物更可溶于第一金属硅化物 。 该层可以通过诸如物理气相沉积，化学气相沉积，蒸发，激光烧蚀或其它沉积方法之类的气相沉积方法形成。 形成硅化物接触的方法包括形成金属层，然后用如上所述的材料注入金属层和/或下层硅层。 在形成金属层之前，材料可以被植入到硅层中。 形成的触点包括第一金属硅化物和在第一金属硅化物中比在第二金属硅化物中更可溶的材料。 触点可以是半导体器件的一部分，其包括衬底，含硅的有源区和设置在有源区上的硅化物触点，并且能够将有源区电耦合到诸如金属化线的其它区域。

公开(公告)号：US08314454B2

公开(公告)日：2012-11-20

申请号：US12970687

申请日：2010-12-16

申请人： Simon S. Chan

发明人： Simon S. Chan

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

公开(公告)号：US07144818B2

公开(公告)日：2006-12-05

申请号：US10729479

申请日：2003-12-05

申请人： Mario M. Pelella ,  Simon S. Chan

发明人： Mario M. Pelella ,  Simon S. Chan

IPC分类号： H01L21/311

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。 衬底利用基层中的沟槽以在层中引起应力。 衬底可以包括硅。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

公开(公告)号：US06291339B1

公开(公告)日：2001-09-18

申请号：US09225218

申请日：1999-01-04

申请人： Steven C. Avanzino ,  Simon S. Chan

发明人： Steven C. Avanzino ,  Simon S. Chan

IPC分类号： H01L214263

CPC分类号： H01L21/76819

摘要： A bilayer interlayer dielectric having a spun-on low k gap filled layer is capped with a higher k dielectric layer. Prior to the capping, the spun-on low k dielectric layer is planarized to reduce or eliminate the systematic variation in the relative thickness of the layers due to pattern density effects on the thickness of the spun-on low k dielectric layer. By removing the variations in the relative thickness of the low k dielectric layer and the capping layer, the effective dielectric constant of the uniformly thick composite interlayer dielectric is independent of location on the circuit, preventing differences in circuit speed and the creation of clock skew in the circuit.

摘要翻译： 具有旋转低k间隙填充层的双层层间电介质用较高的k电介质层封装。 在封盖之前，由于图案密度对纺丝低k电介质层的厚度的影响，使旋转低k电介质层平坦化以减少或消除层的相对厚度的系统变化。 通过去除低k电介质层和覆盖层的相对厚度的变化，均匀厚的复合层间电介质的有效介电常数与电路上的位置无关，防止电路速度的差异和时钟偏差的产生 电路。

公开(公告)号：US6093635A

公开(公告)日：2000-07-25

申请号：US993124

申请日：1997-12-18

申请人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

发明人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  Y10S438/958

摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.

摘要翻译： 无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。 在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

公开(公告)号：US4808273A

公开(公告)日：1989-02-28

申请号：US192343

申请日：1988-05-10

申请人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

发明人： Chang-Hwang Hua ,  Ding-Yuan S. Day ,  Simon S. Chan

IPC分类号： H01L21/74 ,  H01L21/768 ,  C25D5/02

CPC分类号： H01L21/76898

摘要： A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.

摘要翻译： 公开了一种用于在半导体晶片中形成完全金属化的通孔的方法。 金属焊盘与导电互连网络一起形成在半导体晶片的一个面上。 然后沉积绝缘层以覆盖晶片的这个面。 孔在晶片的相对表面被蚀刻，直至并暴露出金属焊盘的一部分。 然后使用金属垫作为阴极，通过电镀将通孔用金属完全填充。

公开(公告)号：US07879718B2

公开(公告)日：2011-02-01

申请号：US11616544

申请日：2006-12-27

申请人： Simon S. Chan

发明人： Simon S. Chan

IPC分类号： H01L21/44

CPC分类号： H01L27/11568 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

摘要翻译： 提供一种用于在半导体存储器件中形成互连的方法。 该方法包括在衬底上形成一对源极选择晶体管。 源区域形成在一对源极选择晶体管之间的衬底中。 在所述一对源极选择晶体管之间形成第一层间电介质。 掩模层沉积在一对源极选择晶体管和层间电介质上，其中掩模层限定了一对源极选择晶体管之间的局部互连区域，其宽度小于一对源选择晶体管之间的距离。 蚀刻半导体存储器件以去除局部互连区域中的第一层间电介质的一部分，从而暴露源极区域。 在局部互连区域中形成金属接触。

公开(公告)号：US07538383B1

公开(公告)日：2009-05-26

申请号：US11416703

申请日：2006-05-03

申请人： Meng Ding ,  Simon S. Chan

发明人： Meng Ding ,  Simon S. Chan

IPC分类号： H01L29/792

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568

摘要： According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segment is situated between the first and second conductive segments. The nitride segment electrically insulates the first conductive segment from the second conductive segment. The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell. The gate stack can further include a lower oxide segment situated between the substrate and the charge-trapping layer. The gate stack can further include an upper oxide segment situated over the charge-trapping layer. The gate stack can be situated between a first dielectric segment and a second dielectric segment, where the first and second dielectric segments are situated over respective first and second bitlines.

摘要翻译： 根据一个示例性实施例，两比特存储器单元包括位于衬底上方的栅极堆叠，其中栅极堆叠包括电荷捕获层。 电荷捕获层包括第一和第二导电段和氮化物区段，其中氮化物区段位于第一和第二导电区段之间。 氮化物区段将第一导电段与第二导电段电绝缘。 第一和第二导电段在双位存储单元中提供相应的第一和第二数据位存储单元。 栅极堆叠还可以包括位于衬底和电荷俘获层之间的较低氧化物段。 栅极堆叠还可以包括位于电荷捕获层上方的上部氧化物段。 栅极堆叠可以位于第一介电段和第二介电段之间，其中第一和第二介电段位于相应的第一和第二位线之上。