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    Method and device using silicide contacts for semiconductor processing
    3.
    发明授权
    Method and device using silicide contacts for semiconductor processing 失效
    使用半导体处理硅化物触点的方法和器件

    公开(公告)号：US06689688B2

    公开(公告)日：2004-02-10

    申请号：US10180858

    申请日：2002-06-25

    申请人： Paul Raymond Besser ,  Simon S. Chan ,  David E. Brown ,  Eric Paton

    发明人： Paul Raymond Besser ,  Simon S. Chan ,  David E. Brown ,  Eric Paton

    IPC分类号： H01L2144

    CPC分类号： H01L21/28518

    摘要： A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide. The contacts may be part of a semiconductor device including a substrate, active region containing silicon, and silicide contacts disposed over the active region and capable of electrically coupling the active region to other regions such as metallization lines.

    摘要翻译： 用于形成硅化物接触的方法包括在诸如源极，漏极和栅极区域的含硅有源器件区域上形成层。 该层包含能够形成一种或多种金属硅化物的金属和可溶于第一金属硅化物但不溶于第二金属硅化物的材料，或者比第二金属硅化物更可溶于第一金属硅化物 。 该层可以通过诸如物理气相沉积，化学气相沉积，蒸发，激光烧蚀或其它沉积方法之类的气相沉积方法形成。 形成硅化物接触的方法包括形成金属层，然后用如上所述的材料注入金属层和/或下层硅层。 在形成金属层之前，材料可以被植入到硅层中。 形成的触点包括第一金属硅化物和在第一金属硅化物中比在第二金属硅化物中更可溶的材料。 触点可以是半导体器件的一部分，其包括衬底，含硅的有源区和设置在有源区上的硅化物触点，并且能够将有源区电耦合到诸如金属化线的其它区域。

    Methods for improved metal gate fabrication
    4.
    发明授权
    Methods for improved metal gate fabrication 失效
    改进金属栅极制造的方法

    公开(公告)号：US06773978B1

    公开(公告)日：2004-08-10

    申请号：US10229690

    申请日：2002-08-28

    申请人： Paul Raymond Besser ,  Eric Paton ,  James Pan

    发明人： Paul Raymond Besser ,  Eric Paton ,  James Pan

    IPC分类号： H01L218242

    CPC分类号： H01L21/28052 ,  H01L21/28097 ,  H01L29/7833

    摘要： Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a polysilicon gate structure while source/drain regions are covered. A second phase conductive metal silicide is formed consuming substantially all of the polysilicon and providing a substantially uniform work function at the silicide/gate oxide interface.

    摘要翻译： 公开了用于制造具有硅化物金属栅极的半导体器件的方法，其中使用单步退火来使诸如钴或镍的金属与基本上所有的多晶硅栅极结构反应，同时覆盖源极/漏极区域。 形成第二相导电金属硅化物，其基本上消耗所有多晶硅，并在硅化物/栅极氧化物界面处提供基本均匀的功函数。

    Semiconductor device having an intermetallic layer on metal interconnects
    5.
    发明授权
    Semiconductor device having an intermetallic layer on metal interconnects 有权
    在金属互连上具有金属间层的半导体器件

    公开(公告)号：US06172421B2

    公开(公告)日：2001-01-09

    申请号：US09132282

    申请日：1998-08-11

    申请人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

    发明人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

    IPC分类号： H01L2348

    CPC分类号： H01L21/76858 ,  H01L21/76849 ,  H01L21/76886

    摘要： The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.

    摘要翻译： 本发明涉及在半导体制造期间在镶嵌金属互连件12的表面上形成保护性金属间化合物层15。 金属间层15防止与互连表面上形成氧化物层有关的问题。 金属间化合物层通过在互连表面上沉积金属而形成，该金属将既减少任何存在的金属氧化物层并与互连金属形成金属间化合物。

    Silicidation with silicon buffer layer and silicon spacers
    6.
    发明授权
    Silicidation with silicon buffer layer and silicon spacers 失效
    用硅缓冲层和硅衬垫硅化

    公开(公告)号：US6100145A

    公开(公告)日：2000-08-08

    申请号：US186073

    申请日：1998-11-05

    申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

    发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656

    摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Field oxide regions, gates, spacers, and source/drain implants are initially formed. A layer of silicon is then deposited. A protective non-contuctive film is then formed and anisotropically etched to expose the silicon layer on the source/drain regions and the top surfaces of the gates, and to form protective spacers on the edges of the field oxide regions and on the side surfaces of the gates. A layer of cobalt is thereafter deposited and silicidation is performed, as by rapid thermal annealing, to form a low-resistance cobalt silicide while consuming the silicon film. The consumption of the silicon film during silicidation results in less consumption of substrate silicon, thereby enabling the formation of ultra-shallow source/drain junctions without junction leakage, allowing the formation of cobalt silicide contacts at optimum thickness and facilitating reliable device scaling.

    摘要翻译： 使用硅化钴接触形成高完整性超浅源极/漏极结。 初始形成场氧化物区域，栅极，间隔物和源/漏植入物。 然后沉积一层硅。 然后形成保护性非导电膜，并进行各向异性蚀刻，以暴露栅极/源极区域和栅极顶表面上的硅层，并在场氧化物区域的边缘和侧表面上形成保护隔离物 大门。 此后沉积一层钴，通过快速热退火进行硅化，以在消耗硅膜的同时形成低电阻的硅化钴。 在硅化期间硅膜的消耗导致较少的衬底硅消耗，从而能够形成没有结漏的超浅源极/漏极结，从而允许以最佳厚度形成钴硅化物触点并促进可靠的器件缩放。

    Semiconductor component and method of manufacture
    8.
    发明授权
    Semiconductor component and method of manufacture 有权
    半导体元件及制造方法

    公开(公告)号：US07319065B1

    公开(公告)日：2008-01-15

    申请号：US10637406

    申请日：2003-08-08

    申请人： Wen Yu ,  Paul Raymond Besser

    发明人： Wen Yu ,  Paul Raymond Besser

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with a metal. The metal is planarized and a dielectric layer is formed over the contact layer. Via extension structures having the same aspect ratio as those in the contact layer are formed in the dielectric layer and aligned with the vias in the contact layer. The vias in the dielectric layer are filled with metal and the metal is planarized. The contact vias in the contact layer and the dielectric layer cooperate to form a composite via structure having the enhanced aspect ratio. Additional dielectric layers having via structures can be included in the composite contact structure to further enhance the aspect ratio of the via structure.

    摘要翻译： 具有增强纵横比的复合通孔结构的半导体部件和半导体部件的制造方法。 具有第一纵横比的通孔形成在设置在半导体衬底上并被金属填充的接触层中。 金属被平坦化，并且在接触层上形成电介质层。 在电介质层中形成具有与接触层相同的纵横比的延伸结构，并与接触层中的通孔对准。 电介质层中的通孔用金属填充，金属被平坦化。 接触层和电介质层中的接触孔合作形成具有增强的纵横比的复合通孔结构。 具有通孔结构的附加电介质层可以包括在复合接触结构中，以进一步增强通孔结构的纵横比。

    Memory device having a nanocrystal charge storage region and method
    10.
    发明授权
    Memory device having a nanocrystal charge storage region and method 有权
    具有纳米晶体电荷存储区域和方法的存储器件

    公开(公告)号：US07309650B1

    公开(公告)日：2007-12-18

    申请号：US11065388

    申请日：2005-02-24

    申请人： Connie Pin-Chin Wang ,  Lu You ,  Zoran Krivokapic ,  Paul Raymond Besser ,  Suzette Keefe Pangrle

    发明人： Connie Pin-Chin Wang ,  Lu You ,  Zoran Krivokapic ,  Paul Raymond Besser ,  Suzette Keefe Pangrle

    IPC分类号： H01L21/44

    CPC分类号： H01L29/7833 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332

    摘要： A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.

    摘要翻译： 一种具有金属纳米晶体电荷存储结构的存储器件及其制造方法。 存储器件可以通过在半导体衬底上形成第一氧化物层，然后在氧化物层上设置多孔介电层并在第二氧化物层上设置第二氧化物层来制造。 在第二介电材料层上形成一层导电材料。 在导电材料上形成蚀刻掩模。 导电材料和下面的介电层被各向异性地蚀刻以形成其上设置有栅电极的电介质结构。 在介电结构和栅电极上形成金属层，并处理金属层的一部分扩散到多孔介电层中。 然后去除金属层。