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公开(公告)号：US20190087250A1
公开(公告)日：2019-03-21
申请号：US16174557
申请日：2018-10-30
Applicant: Everspin Technologies, Inc.
Inventor： Jon SLAUGHTER , Dimitri HOUSSAMEDDINE , Thomas ANDRE , Syed M. ALAM
Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.
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公开(公告)号：US20230026294A1
公开(公告)日：2023-01-26
申请号：US17652905
申请日：2022-02-28
Applicant: Everspin Technologies, Inc.
Inventor： Dimitri HOUSSAMEDDINE , Syed M. ALAM , Sanjeev AGGARWAL
IPC: H03K19/1776 , G11C11/16 , G11C13/00 , H03K19/17724 , H03K19/17784
Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.
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公开(公告)号：US20230281434A1
公开(公告)日：2023-09-07
申请号：US17893462
申请日：2022-08-23
Applicant: Everspin Technologies, Inc.
Inventor： Syed M. ALAM , Dimitri HOUSSAMEDDINE , Sanjeev AGGARWAL
CPC classification number: G06N3/063 , G11C11/54 , G11C11/161
Abstract: The present disclosure is drawn to, among other things, a device comprising input circuitry; weight operation circuitry electrically connected to the input circuitry; bias operation circuitry electrically connected to the weight operation circuitry; storage circuitry electrically connected to the weight operation circuitry and the bias operation circuitry; and activation function circuitry electrically connected to the bias operation circuitry, wherein at least the weight operation circuitry, the bias operation circuitry, and the storage circuitry are located on a same chip.
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公开(公告)号：US20190123268A1
公开(公告)日：2019-04-25
申请号：US16230031
申请日：2018-12-21
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Renu WHIG , Jijun SUN , Nicholas RIZZO , Jon SLAUGHTER , Dimitri HOUSSAMEDDINE , Frederick MANCOFF
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
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公开(公告)号：US20180122495A1
公开(公告)日：2018-05-03
申请号：US15852678
申请日：2017-12-22
Applicant: Everspin Technologies Inc.
Inventor： Thomas ANDRE , Jon SLAUGHTER , Dimitri HOUSSAMEDDINE , Syed M. ALAM
CPC classification number: G11C29/50 , G06F11/08 , G06F11/1048 , G11C11/1673 , G11C2029/0411
Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
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Patent Agency Ranking
公开(公告)号：US20170263300A1
公开(公告)日：2017-09-14
申请号：US15605508
申请日：2017-05-25
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Thomas ANDRE , Dimitri HOUSSAMEDDINE , Syed M. ALAM , Jon SLAUGHTER , Chitra SUBRAMANIAN
IPC: G11C11/16 , G06F12/0804
CPC classification number: G11C11/1675 , G06F12/0804 , G11C11/1677 , Y02D10/13
Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
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公开(公告)号：US20240006011A1
公开(公告)日：2024-01-04
申请号：US18467996
申请日：2023-09-15
Applicant: Everspin Technologies, Inc.
Inventor： Syed M. ALAM , Jason JANESKY , Han Kyu LEE , Hamid ALMASI , Pedro SANCHEZ , Cristian P. MASGRAS , Iftekhar RAHMAN , Sumio IKEGAWA , Sanjeev AGGARWAL , Dimitri HOUSSAMEDDINE , Frederick Charles NEUMEYER
CPC classification number: G11C29/42 , G11C29/1201 , G11C2029/0407 , G11C29/4401 , G11C29/18
Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
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公开(公告)号：US20230378958A1
公开(公告)日：2023-11-23
申请号：US18362704
申请日：2023-07-31
Applicant: Everspin Technologies, Inc.
Inventor： Dimitri HOUSSAMEDDINE , Syed M. ALAM , Sanjeev AGGARWAL
IPC: H03K19/1776 , G11C13/00 , H03K19/17784 , G11C11/16 , H03K19/17724 , G06F21/78
CPC classification number: H03K19/1776 , G11C13/0069 , H03K19/17784 , G11C11/1675 , H03K19/17724 , G06F21/78
Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.
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公开(公告)号：US20220139488A1
公开(公告)日：2022-05-05
申请号：US17512392
申请日：2021-10-27
Applicant: Everspin Technologies, Inc.
Inventor： Syed M. ALAM , Jason JANESKY , Han Kyu LEE , Hamid ALMASI , Pedro SANCHEZ , Cristian P. MASGRAS , Iftekhar RAHMAN , Sumio IKEGAWA , Sanjeev AGGARWAL , Dimitri HOUSSAMEDDINE , Frederick Charles NEUMEYER
Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.
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公开(公告)号：US20190386212A1
公开(公告)日：2019-12-19
申请号：US16551952
申请日：2019-08-27
Applicant: Everspin Technologies, Inc.
Inventor： Renu WHIG , Jijun SUN , Nicholas RIZZO , Jon SLAUGHTER , Dimitri HOUSSAMEDDINE , Frederick MANCOFF
Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
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