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公开(公告)号：US20150211470A1
公开(公告)日：2015-07-30
申请号：US14166891
申请日：2014-01-29
发明人： Adriano Marques Pereira , Sunny Gupta , Andre Luis Vilas Boas , Pedro Barbosa Zanetta , Ivan Carlos Ribeiro Nascimento , Carl Culshaw
IPC分类号： F02N11/08
CPC分类号： F02N11/0862 , F02N2200/063 , F02N2250/02
摘要： Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.
摘要翻译： 用于管理冷曲轴事件的系统和方法。 在一个实施例中，方法可以包括检测冷曲轴事件并将开关电路设置为非导通状态，其中开关电路被配置为将第一调节器耦合到存储器电路，使得将开关电路设置为非导通状态 存储电路与第一调节器解耦。 该方法还可以包括在冷启动事件之后的恢复周期期间将开关电路设置为电流限制模式中的导通状态，以将存储器电路重新耦合到第一调节器。 在另一个实施例中，电子设备包括开关电路，耦合到开关电路的第一端子的第一调节器，耦合到开关电路的第二端子的第二调节器，耦合到开关电路的逻辑电路和存储器 电路耦合到开关电路的第二端子。
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公开(公告)号：US10216452B2
公开(公告)日：2019-02-26
申请号：US15210567
申请日：2016-07-14
摘要： An apparatus embodiment includes an integrated circuit (IC) and breach-detection circuitry. The IC includes data storage circuitry, a power grid configured to distribute power to the data storage circuitry, and a plurality of nodes distributed over at least one sensitive region of the IC. The breach-detection circuitry monitors power grid integrity at the at least one sensitive region of the IC and detects an event indicative of a breach by an external probe at a portion of the at least one sensitive region in response to floating node detection or a change in voltage at one of the plurality of nodes.
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公开(公告)号：US09356569B2
公开(公告)日：2016-05-31
申请号：US14057886
申请日：2013-10-18
发明人： Andre Luis Vilas Boas , Edevaldo Pereira Silva, Jr. , Pedro Barbosa Zanetta , Eduardo Ribeiro da Silva
CPC分类号： H03F3/45192 , G05F3/30 , H03F1/301 , H03F2200/447 , H03F2203/45538
摘要： Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.
摘要翻译： 差分放大器的就绪标志电路。 在一些实施例中，半导体器件可以包括具有两个输入的放大器和可操作地耦合到放大器的就绪标志电路，准备标志电路被配置为监视放大器的两个或更多个内部节点并产生指示是否 两个输入之间的电压或电流差已被最小化。 在其他实施例中，一种方法可以包括经由就绪标志电路监测差分放大器的第一和第二内部节点，其中差分放大器是带隙电压参考电路的一部分，并且经由就绪标志电路 指示带隙电压基准电路的输出是否已经达到标称值的信号。
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公开(公告)号：US20150109054A1
公开(公告)日：2015-04-23
申请号：US14057886
申请日：2013-10-18
发明人： Andre Luis Vilas Boas , Edevaldo Pereira Silva, JR. , Pedro Barbosa Zanetta , Eduardo Ribeiro da Silva
CPC分类号： H03F3/45192 , G05F3/30 , H03F1/301 , H03F2200/447 , H03F2203/45538
摘要： Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.
摘要翻译： 差分放大器的就绪标志电路。 在一些实施例中，半导体器件可以包括具有两个输入的放大器和可操作地耦合到放大器的就绪标志电路，准备标志电路被配置为监视放大器的两个或更多个内部节点并产生指示是否 两个输入之间的电压或电流差已被最小化。 在其他实施例中，一种方法可以包括经由就绪标志电路监测差分放大器的第一和第二内部节点，其中差分放大器是带隙电压参考电路的一部分，并且经由就绪标志电路 指示带隙电压基准电路的输出是否已经达到标称值的信号。
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公开(公告)号：US20180018125A1
公开(公告)日：2018-01-18
申请号：US15210567
申请日：2016-07-14
IPC分类号： G06F3/06
CPC分类号： G06F3/0652 , G06F3/0623 , G06F3/064 , G06F3/0679 , G06F21/86 , H01L23/57 , Y04S40/24
摘要： An apparatus embodiment includes an integrated circuit (IC) and breach-detection circuitry. The IC includes data storage circuitry, a power grid configured to distribute power to the data storage circuitry, and a plurality of nodes distributed over at least one sensitive region of the IC. The breach-detection circuitry monitors power grid integrity at the at least one sensitive region of the IC and detects an event indicative of a breach by an external probe at a portion of the at least one sensitive region in response to floating node detection or a change in voltage at one of the plurality of nodes.
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公开(公告)号：US09680453B1
公开(公告)日：2017-06-13
申请号：US15231916
申请日：2016-08-09
IPC分类号： H03L7/00 , H03K4/501 , H03L7/089 , H03L7/099 , H03K5/13 , H03K5/131 , H03K3/0231 , H03B5/24 , H03K5/00
CPC分类号： H03K4/501 , H03B5/24 , H03K3/0231 , H03K5/13 , H03K5/131 , H03K2005/00065 , H03L7/00 , H03L7/08 , H03L7/089 , H03L7/099
摘要： Aspects of various embodiments of the present disclosure are directed to applications utilizing oscillator circuits. In certain embodiments, an apparatus includes an oscillator circuit having one or more capacitors. The oscillator circuit is configured to generate an oscillating signal by repeated charging and discharging of the capacitors. The apparatus also includes a control circuit connected to the oscillator. The control circuit is configured to set the oscillation frequency of the oscillator circuit as a non-linear function of an input control signal. For instance, in a more specific embodiment, the control circuit may be configured to set oscillation frequency of the oscillator circuit to a frequency scaled by a value raised to an exponent specified by the input control signal.
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公开(公告)号：US09645196B2
公开(公告)日：2017-05-09
申请号：US13684840
申请日：2012-11-26
CPC分类号： G01R31/2884 , G01R31/2896
摘要： A test structure (200) in an integrated circuit (100) includes a probe pad (210) disposed at a surface of a die (102) of the integrated circuit, a transmission gate (202) for connecting portions of an electronic circuit within the integrated circuit in response to a momentary signal applied to the probe pad, a first inverter (221) having an input coupled to the probe pad and having an output coupled to a control input of the transmission gate, and a second inverter (222) having an input coupled to an output of the first inverter and having an output coupled to another control input of the transmission gate. The output of the second inverter is coupled to the input of the first inverter. Upon power-up, the transmission gate is open. After the momentary signal is applied to the probe pad, the transmission gate closes and remains closed until power is disconnected.
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公开(公告)号：US09644593B2
公开(公告)日：2017-05-09
申请号：US14166891
申请日：2014-01-29
发明人： Adriano Marques Pereira , Sunny Gupta , Andre Luis Vilas Boas , Pedro Barbosa Zanetta , Ivan Carlos Ribeiro Nascimento , Carl Culshaw
CPC分类号： F02N11/0862 , F02N2200/063 , F02N2250/02
摘要： Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.
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公开(公告)号：US09143115B2
公开(公告)日：2015-09-22
申请号：US14639795
申请日：2015-03-05
CPC分类号： H03K3/012 , H02M1/08 , H03K17/04123
摘要： An integrated circuit includes a delay compensation circuit (221, 222) that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.
摘要翻译： 集成电路包括延迟补偿电路（221,222），其还包括用于从集成电路外部的电路接收变化信号的端子; 采样器电路，其在数字信号中每次出现转换时采样和保持变化信号的当前值; 耦合到采样器电路的积分器，其对变化信号的采样和参考信号之间的电压差进行积分，并且输出积分的结果，其中积分器的时间常数大于变化信号的周期 ; 波形发生器，其响应于第二数字信号中的转变而产生降低的电压; 以及具有用于接收降低电压的一个输入端子，用于接收结果的反相输入端子和用于输出产生输出信号的信号的输出端子的比较器。
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