公开(公告)号：US09767875B2

公开(公告)日：2017-09-19

申请号：US14823825

申请日：2015-08-11

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Thomas Jew

IPC: G11C11/16 ,  G11C29/02

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C29/026 ,  G11C29/028

Abstract: A method uses a memory that includes a plurality of non-volatile memory (NVM) cells; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input includes. A reference is coupled to the non-inverting input. The output of the amplifier is coupled to the inverting input of the amplifier while the non-inverting input receives the reference. The output is decoupled from the inverting input to store a voltage on the inverting input of the amplifier. A non-volatile (NV) element of a first NVM cell of the plurality of NVM cells is coupled to the non-inverting input. An output signal representative of the state of the NVM cell is provided.

公开(公告)号：US20170047101A1

公开(公告)日：2017-02-16

申请号：US14823825

申请日：2015-08-11

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Thomas Jew

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C29/026 ,  G11C29/028

Abstract: A method uses a memory that includes a plurality of non-volatile memory (NVM) cells; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input includes. A reference is coupled to the non-inverting input. The output of the amplifier is coupled to the inverting input of the amplifier while the non-inverting input receives the reference. The output is decoupled from the inverting input to store a voltage on the inverting input of the amplifier. A non-volatile (NV) element of a first NVM cell of the plurality of NVM cells is coupled to the non-inverting input. An output signal representative of the state of the NVM cell is provided.

Abstract translation: 一种方法使用包括多个非易失性存储器（NVM）单元的存储器; 多个字线; 多个位线; 以及具有反相输入，非反相输入和输出的放大器; 并且耦合到反相输入的电容包括。 参考连接到非反相输入。 放大器的输出端连接到放大器的反相输入端，同相输入端接收参考电压。 输出与反相输入端分离，以在放大器的反相输入端存储电压。 多个NVM单元中的第一NVM单元的非易失性（NV）元件耦合到非反相输入。 提供表示NVM单元的状态的输出信号。

公开(公告)号：US09508397B1

公开(公告)日：2016-11-29

申请号：US14957778

申请日：2015-12-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Richard K. Eguchi ,  Thomas Jew ,  Craig T. Swift

IPC: G11C16/10 ,  G11C5/14 ,  G11C7/06

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/28 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C2029/0409

Abstract: An operating voltage and reference current are adjusted in a memory device. At least a portion of an array of memory cells is preconditioned to an erased state using an erase verify voltage on word lines coupled to the memory cells and a first reference current in sense amplifiers coupled to bit lines for the array. A test reference current is set for the sense amplifiers. A bitcell gate voltage is set on the word lines to a present overdrive voltage. The at least a portion of the array is read. If any of the memory cells in the at least a portion of the array are read as being programmed, the present overdrive voltage is increased until none of the memory cells in the at least a portion of the array are read as being programmed.

Abstract translation: 在存储器件中调节工作电压和参考电流。 使用耦合到存储器单元的字线上的擦除验证电压和耦合到阵列的位线的读出放大器中的第一参考电流，将存储器单元阵列的至少一部分预处理为擦除状态。 为读出放大器设置测试参考电流。 字元栅极电压在字线上设置为当前的过驱动电压。 读取阵列的至少一部分。 如果阵列的至少一部分中的任何存储器单元被读取为被编程，则增加当前的过驱动电压，直到阵列的至少一部分中的存储单元都不被读取为被编程为止。

公开(公告)号：US09651617B2

公开(公告)日：2017-05-16

申请号：US14866094

申请日：2015-09-25

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Edward Bryann C. Fernandez ,  David W. Chrudimsky ,  Thomas Jew

IPC: G01R31/28 ,  G01R31/317 ,  G11C29/36 ,  G11C29/38 ,  G06F11/27

CPC classification number: G01R31/31724 ,  G06F11/27 ,  G11C29/36 ,  G11C29/38

Abstract: Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.

公开(公告)号：US09349426B1

公开(公告)日：2016-05-24

申请号：US14741674

申请日：2015-06-17

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Thomas Jew

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/00 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0073 ,  G11C2213/78 ,  G11C2213/79 ,  G11C2213/82

Abstract: A non-volatile memory device includes an array of non-volatile (NV) memory cells organized in pairs. Each pair is included with a transistor to form a memory unit. Each unit is coupled to a bit line, a word line, and a pair of source lines. The NV elements are programmable to either a relatively high resistance or relatively low resistance and the particularly resistance is established, by converting one resistance type to the other or maintaining the existing resistance type the direction of current through the NV element. A bit is formed from two NV cells in different memory units which are programmed to different resistance types and thereby provide a differential pair from which the logic state of the bit can be determined.

Abstract translation: 非易失性存储器件包括成对组织的非易失性（NV）存储器单元的阵列。 每对都包括在晶体管中以形成存储单元。 每个单元耦合到位线，字线和一对源极线。 NV元件可编程为相对较高的电阻或相对较低的电阻，并且通过将一个电阻类型转换为另一个或将现有电阻类型保持通过NV元件的电流的方向而建立特别的电阻。 由不同存储器单元中的两个NV单元形成位，其被编程为不同的电阻类型，从而提供差分对，从而可以确定位的逻辑状态。

公开(公告)号：US10007588B2

公开(公告)日：2018-06-26

申请号：US15005537

申请日：2016-01-25

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Botang Shao ,  Timothy J. Strauss ,  Thomas Jew ,  Edward Bryann C. Fernandez

IPC: G06F11/00 ,  G06F11/27 ,  G06F11/263 ,  G06F11/273 ,  G11C29/14 ,  G11C29/18 ,  G11C29/12

CPC classification number: G06F11/27 ,  G06F11/263 ,  G06F11/273 ,  G11C29/14 ,  G11C29/18 ,  G11C2029/1206

Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

公开(公告)号：US09558800B2

公开(公告)日：2017-01-31

申请号：US14788273

申请日：2015-06-30

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Thomas Jew

IPC: G11C5/06 ,  G11C11/16 ,  G11C11/15

CPC classification number: G11C11/15 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. A memory cell in the array of memory cells includes a first resistive element including a first terminal and a second terminal, a second resistive element including a first terminal and a second terminal, and a select transistor including a gate electrode coupled to a word line, a first current electrode coupled to the first terminal of the first resistive element and the first terminal of the second resistive element, and a second current electrode coupled to a bit line. The second terminal of the first resistive element is coupled to a first source line, and the second terminal of the second resistive element is coupled to a second source line.

Abstract translation: 非易失性存储器件包括非易失性存储器单元阵列。 存储单元阵列中的存储单元包括包括第一端子和第二端子的第一电阻元件，包括第一端子和第二端子的第二电阻元件，以及包括耦合到字线的栅电极的选择晶体管， 耦合到第一电阻元件的第一端子和第二电阻元件的第一端子的第一电流电极和耦合到位线的第二电流电极。 第一电阻元件的第二端子耦合到第一源极线，并且第二电阻元件的第二端子耦合到第二源极线。