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    FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR
    1.
    发明申请
    FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR 有权
    使用多时钟发生器的过滤器自动校准

    公开(公告)号：US20120098592A1

    公开(公告)日：2012-04-26

    申请号：US12910232

    申请日：2010-10-22

    申请人： Feng Wei Kuo ,  Mei-Show Chen ,  Chewn-Pu Jou ,  Ying-Ta Lu ,  Jia-Liang Chen

    发明人： Feng Wei Kuo ,  Mei-Show Chen ,  Chewn-Pu Jou ,  Ying-Ta Lu ,  Jia-Liang Chen

    IPC分类号： H03J3/02 ,  H03L7/00

    CPC分类号： H03H21/0067 ,  H03D3/007 ,  H03H2021/0081 ,  H03H2210/04 ,  H03J2200/08 ,  H03L7/07 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/193 ,  H03L7/1976 ,  H04B1/30

    摘要： A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module.

    摘要翻译： 滤波器自动校准系统包括多时钟模块。 多时钟模块包括多时钟发生器，其被配置为基于通道设置产生具有可变频率的时钟信号。 至少有一个要校准的过滤器。 自动校准控制模块被配置为基于通道设置来控制至少一个滤波器的校准。 多时钟模块被配置为将可变频率时钟信号提供给至少一个滤波器和自动校准控制模块，并且至少一个滤波器耦合到自动校准控制模块。

    Method and apparatus for efficient time slicing
    3.
    发明授权
    Method and apparatus for efficient time slicing 有权
    高效时间切片的方法和装置

    公开(公告)号：US08436686B2

    公开(公告)日：2013-05-07

    申请号：US12885974

    申请日：2010-09-20

    申请人： Feng Wei Kuo ,  Ying-Ta Lu ,  Chewn-Pu Jou

    发明人： Feng Wei Kuo ,  Ying-Ta Lu ,  Chewn-Pu Jou

    IPC分类号： H03L7/00

    CPC分类号： H03L7/087 ,  H03L7/1974 ,  H03L7/235

    摘要： Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit.

    摘要翻译： 一种用于高效时间分片的装置，包括具有压控振荡器的锁相环电路，与锁相环电路耦合的自动频率校准电路，其被配置为输出选择压控振荡器的范围的值，以及突发模式检测器 与自动频率校准电路连接。 突发模式检测器具有适于存储自动频率校准电路的输出的寄存器。

    Method and apparatus for amplifying a time difference
    4.
    发明授权
    Method and apparatus for amplifying a time difference 有权
    用于放大时差的方法和装置

    公开(公告)号：US08476972B2

    公开(公告)日：2013-07-02

    申请号：US12813620

    申请日：2010-06-11

    申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC分类号： G06G7/12 ,  G06G7/26

    CPC分类号： G04F10/005

    摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

    摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。

    Auto frequency calibration for a phase locked loop and method of use
    5.
    发明授权
    Auto frequency calibration for a phase locked loop and method of use 有权
    锁相环的自动频率校准和使用方法

    公开(公告)号：US08953730B2

    公开(公告)日：2015-02-10

    申请号：US13452138

    申请日：2012-04-20

    申请人： Yen-Jen Chen ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    发明人： Yen-Jen Chen ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.

    摘要翻译： 锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。 锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。 锁相环包括配置为接收相位差信号并输出​​微调信号的数字环路滤波器。 锁相环包括配置成接收粗调和微调信号并输出​​输出频率的压控振荡器。 锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。 锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。

    Band pass filter for 2.5D/3D integrated circuit applications
    7.
    发明授权
    Band pass filter for 2.5D/3D integrated circuit applications 有权
    2.5D / 3D集成电路应用的带通滤波器

    公开(公告)号：US09275923B2

    公开(公告)日：2016-03-01

    申请号：US13557457

    申请日：2012-07-25

    申请人： Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou ,  Shuo-Mao Chen ,  Der-Chyang Yeh

    发明人： Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou ,  Shuo-Mao Chen ,  Der-Chyang Yeh

    IPC分类号： H05K7/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64 ,  H01L23/66 ,  H01L25/16 ,  H01L23/00

    CPC分类号： H01L23/3128 ,  H01L23/642 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2223/6627 ,  H01L2223/6672 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/00

    摘要： Some embodiments relate to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip includes a plurality of capacitors embedded in a common molding compound along with a transceiver chip. The integrated passive device chip and the transceiver chip are also arranged within a polymer package. An ultra-thick metallization layer is disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layer also forms a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area as compared to conventional solutions.

    摘要翻译： 一些实施例涉及一种带通滤波器的器件和方法，其具有相对于当前解决方案的降低的成本，面积损失和制造复杂性。 集成的无源器件芯片包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片。 集成无源器件芯片和收发器芯片也布置在聚合物封装内。 超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。 超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积的带通滤波器。

    Phase frequency detector circuit
    9.
    发明授权
    Phase frequency detector circuit 有权
    相位检波电路

    公开(公告)号：US08643402B2

    公开(公告)日：2014-02-04

    申请号：US13308274

    申请日：2011-11-30

    申请人： Yen-Jen Chen ,  I-Ting Lee ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    发明人： Yen-Jen Chen ,  I-Ting Lee ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    IPC分类号： H03D13/00 ,  H03D3/00

    CPC分类号： H03D13/00 ,  H03D13/004 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10

    摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

    摘要翻译： 相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。 边缘检测器电路被配置为接收第一输入信号和第二输入信号。 判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。 响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

    Lock detector and method of detecting lock status for phase lock loop
    10.
    发明授权
    Lock detector and method of detecting lock status for phase lock loop 有权
    锁定检测器和检测锁相环锁定状态的方法

    公开(公告)号：US08456207B1

    公开(公告)日：2013-06-04

    申请号：US13297658

    申请日：2011-11-16

    申请人： Feng Wei Kuo ,  Kyle Yen ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

    发明人： Feng Wei Kuo ,  Kyle Yen ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095

    摘要： A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.

    摘要翻译： 用于PLL电路的锁定检测器包括第一信号计数电路，第二信号计数电路，比较器和锁定状态单元。 第一信号计数电路被配置为根据第一振荡信号和预定周期值来定义多个观察周期。 第二信号计数电路被配置为根据每个观测周期内的第二振荡信号来确定最大计数器值，并且相对于第一振荡信号产生第二振荡信号。 比较器被配置为为每个观察周期确定最大计数器值是否等于预定周期值。 锁定状态单元被配置为基于最大计数器值等于预定数量的连续观察周期中的预定周期值的锁定信号。