公开(公告)号：US07749860B2

公开(公告)日：2010-07-06

申请号：US09392034

申请日：1999-09-08

申请人： Fernando Gonzalez ,  David Chapek ,  Ranshir P. S. Thakur

发明人： Fernando Gonzalez ,  David Chapek ,  Ranshir P. S. Thakur

IPC分类号： H01L21/764 ,  H01L29/00

CPC分类号： H01L21/76237

摘要： The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal layer is formed substantially conformably over the spacer, over the remaining portions of the first dielectric layer, and substantially filling the isolation trench. Planarization of the conformal layer follows, either by CMP or by etchback or by a combination thereof. An isolation trench filled with a structure results. The resulting structure has a flange and shaft, the cross-section of which has a nail shape in cross-section.

摘要翻译： 本发明涉及一种用于在半导体衬底中形成隔离沟槽结构的方法，而不会在其上表面造成有害的地形凹陷，这导致电流和电荷泄漏到相邻的有效区域。 本发明的方法在半导体衬底上形成衬垫氧化物，然后在衬底氧化物上形成氮化物层。 用掩模对氮化物层进行图案化并蚀刻以暴露焊盘氧化物层的一部分并保护半导体衬底中保留被氮化物层覆盖的有源区。 第二电介质层基本上顺应地形成在焊盘氧化物层和第一电介质层的剩余部分上。 然后进行间隔物蚀刻以从第二介电层形成间隔物。 间隔物与第一电介质层的剩余部分接触。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 在第一介电层的剩余部分上基本上顺应地形成保形层，并基本上填充隔离沟槽。 通过CMP或通过回蚀或其组合，可以平铺保形层。 填充结构的隔离沟槽结果。 所得到的结构具有法兰和轴，其横截面具有指甲形状的横截面。

公开(公告)号：US5953621A

公开(公告)日：1999-09-14

申请号：US985588

申请日：1997-12-05

申请人： Fernando Gonzalez ,  David Chapek ,  Randhir P. S. Thakur

发明人： Fernando Gonzalez ,  David Chapek ,  Randhir P. S. Thakur

IPC分类号： H01L21/762

CPC分类号： H01L21/76237

摘要： The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal layer is formed substantially conformably over the spacer, over the remaining portions of the first dielectric layer, and substantially filling the isolation trench. Planarization of the conformal layer follows, either by CMP or by etchback or by a combination thereof. An isolation trench filled with a structure results. The resulting structure has a flange and shaft, the cross section of which has a nail shape in cross section.

摘要翻译： 本发明涉及一种用于在半导体衬底中形成隔离沟槽结构的方法，而不会在其上表面造成有害的地形凹陷，这导致电流和电荷泄漏到相邻的有效区域。 本发明的方法在半导体衬底上形成衬垫氧化物，然后在衬底氧化物上形成氮化物层。 用掩模对氮化物层进行图案化并蚀刻以暴露焊盘氧化物层的一部分并保护半导体衬底中保留被氮化物层覆盖的有源区。 第二电介质层基本上顺应地形成在焊盘氧化物层和第一电介质层的剩余部分上。 然后进行间隔物蚀刻以从第二介电层形成间隔物。 间隔物与第一电介质层的剩余部分接触。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 在第一介电层的剩余部分上基本上顺应地形成保形层，并基本上填充隔离沟槽。 通过CMP或通过回蚀或其组合，可以平铺保形层。 填充结构的隔离沟槽结果。 所得到的结构具有法兰和轴，其横截面具有指甲形状。

公开(公告)号：US20120208345A1

公开(公告)日：2012-08-16

申请号：US13454187

申请日：2012-04-24

申请人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

发明人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

IPC分类号： H01L21/762

CPC分类号： H01L21/76237

摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

摘要翻译： 本发明涉及在半导体衬底中形成微电子结构的方法。 该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。 绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。 间隔物可以由绝缘材料形成。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。 保形材料的平面化可能遵循。

公开(公告)号：US6097076A

公开(公告)日：2000-08-01

申请号：US823609

申请日：1997-03-25

申请人： Fernando Gonzalez ,  David Chapek ,  Randhir P. S. Thakur

发明人： Fernando Gonzalez ,  David Chapek ,  Randhir P. S. Thakur

IPC分类号： H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76237

摘要： The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal layer is formed substantially conformably over the spacer, over the remaining portions of the first dielectric layer, and substantially filling the isolation trench. Planarization of the conformal layer follows, either by CMP or by etchback or by a combination thereof. An isolation trench filled with a structure results. The resulting structure has a flange and shaft, the cross section of which has a nail shape in cross section.

摘要翻译： 本发明涉及一种用于在半导体衬底中形成隔离沟槽结构的方法，而不会在其上表面造成有害的地形凹陷，这导致电流和电荷泄漏到相邻的有效区域。 本发明的方法在半导体衬底上形成衬垫氧化物，然后在衬底氧化物上形成氮化物层。 用掩模对氮化物层进行图案化并蚀刻以暴露焊盘氧化物层的一部分并保护半导体衬底中保留被氮化物层覆盖的有源区。 第二电介质层基本上顺应地形成在焊盘氧化物层和第一电介质层的剩余部分上。 然后进行间隔物蚀刻以从第二介电层形成间隔物。 间隔物与第一电介质层的剩余部分接触。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 在第一介电层的剩余部分上基本上顺应地形成保形层，并基本上填充隔离沟槽。 通过CMP或通过回蚀或其组合，可以平铺保形层。 填充结构的隔离沟槽结果。 所得到的结构具有法兰和轴，其横截面具有指甲形状。

公开(公告)号：US20100273309A1

公开(公告)日：2010-10-28

申请号：US12828868

申请日：2010-07-01

申请人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

发明人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

IPC分类号： H01L21/762

CPC分类号： H01L21/76237

摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

摘要翻译： 本发明涉及在半导体衬底中形成微电子结构的方法。 该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。 绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。 间隔物可以由绝缘材料形成。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。 保形材料的平面化可能遵循。

公开(公告)号：US08451650B2

公开(公告)日：2013-05-28

申请号：US13524809

申请日：2012-06-15

申请人： Fernando Gonzalez ,  Chandra V. Mouli

发明人： Fernando Gonzalez ,  Chandra V. Mouli

IPC分类号： G11C11/24

CPC分类号： G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US08374037B2

公开(公告)日：2013-02-12

申请号：US13186796

申请日：2011-07-20

申请人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

发明人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

IPC分类号： G11C16/10

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C16/0483 ,  H01L27/11521

摘要： A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

摘要翻译： 半导体磁存储器件具有形成在存储单元上的磁性隧道结。 存储单元具有由浮动栅极包围的控制门。 浮动栅极通过钉扎层耦合到磁性隧道结，该钉扎层保持结的下部磁性层的磁性取向。 耦合到控制栅极的选定字线的电流产生第一磁场。 通过单元选择线的电流产生与第一磁场正交的第二磁场。 这改变了结的上部磁性层的磁性取向以降低其电阻，从而允许编程/擦除线上的写入/擦除电压对浮动栅极进行编程/擦除。

公开(公告)号：US20120258577A1

公开(公告)日：2012-10-11

申请号：US13524809

申请日：2012-06-15

申请人： Fernando Gonzalez ,  Chandra V. Mouli

发明人： Fernando Gonzalez ,  Chandra V. Mouli

IPC分类号： H01L21/8239

CPC分类号： G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US20110080783A1

公开(公告)日：2011-04-07

申请号：US12966430

申请日：2010-12-13

申请人： Parag Banerjee ,  Terry Grafron ,  Fernando Gonzalez

发明人： Parag Banerjee ,  Terry Grafron ,  Fernando Gonzalez

IPC分类号： G11C11/15

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C16/0483 ,  H01L27/11521

摘要： A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

摘要翻译： 半导体磁存储器件具有在存储单元上形成的磁隧道结。 存储单元具有由浮动栅极包围的控制栅极。 浮动栅极通过钉扎层耦合到磁性隧道结，该钉扎层保持结的下部磁性层的磁性取向。 耦合到控制栅极的选定字线的电流产生第一磁场。 通过单元选择线的电流产生与第一磁场正交的第二磁场。 这改变了结的上部磁性层的磁性取向以降低其电阻，从而允许编程/擦除线上的写入/擦除电压对浮动栅极进行编程/擦除。

公开(公告)号：US07563666B2

公开(公告)日：2009-07-21

申请号：US11869012

申请日：2007-10-09

申请人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung Tri Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

发明人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung Tri Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

IPC分类号： H01L21/8234

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

摘要翻译： 提供了制造垂直二极管结构的半导体结构和方法。 垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。 硅化钛层可以形成在二极管开口的内表面上并与活性区接触。 二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。 硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。 顶部可以由底部限定，以便不与硅化钛层接触。 在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。