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    FeRAM sidewall diffusion barrier etch
    1.
    发明授权
    FeRAM sidewall diffusion barrier etch 有权
    FeRAM侧壁扩散阻挡蚀刻

    公开(公告)号：US06713342B2

    公开(公告)日：2004-03-30

    申请号：US10282759

    申请日：2002-10-29

    申请人： Francis G. Celii ,  Scott R. Summerfelt ,  Tomoyuki Sakoda ,  Chiu Chi

    发明人： Francis G. Celii ,  Scott R. Summerfelt ,  Tomoyuki Sakoda ,  Chiu Chi

    IPC分类号： H01L218242

    CPC分类号： H01L21/31122 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

    摘要翻译： 本发明涉及一种形成FeRAM集成电路的方法，其包括在蚀刻底部电极扩散阻挡层之前形成侧壁扩散阻挡层。 然后在底部电极扩散阻挡层之前蚀刻侧壁扩散阻挡层。 在蚀刻下面的底部电极扩散阻挡层之前，在构图AlOx侧壁扩散阻挡层之前，蚀刻化学性质包括BCl 3 + Ar。 BCl3在相邻的电容器堆叠之间的电容器堆叠（例如TiAlN）和氮化物底部电极扩散阻挡层（例如，具有小的氧含量的TiAlON）的顶部上对下面的氮化物硬掩模具有良好的选择性是有效的。 可以将Ar添加到蚀刻化学品中，因为所得到的表面（硬掩模和底部电极扩散屏障的顶部）更平滑。

    METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD
    3.
    发明申请
    METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD 审中-公开
    用于蚀刻基板的方法和使用该方法形成的器件

    公开(公告)号：US20080303141A1

    公开(公告)日：2008-12-11

    申请号：US12137692

    申请日：2008-06-12

    申请人： K.R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, JR. ,  Francis G. Celii

    发明人： K.R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, JR. ,  Francis G. Celii

    IPC分类号： H01L23/535

    CPC分类号： H01L21/31116 ,  H01L21/31616 ,  H01L21/76895 ,  H01L28/55

    摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

    摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其它步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，蚀刻剂对氧化铝蚀刻停止层130是选择性的。氧化铝蚀刻停止层也可以用于 高级CMOS工艺的后端作为通孔蚀刻停止层。

    FeRAM capacitor stack etch
    4.
    发明授权
    FeRAM capacitor stack etch 有权
    FeRAM电容堆栈蚀刻

    公开(公告)号：US07029925B2

    公开(公告)日：2006-04-18

    申请号：US10968721

    申请日：2004-10-19

    申请人： Francis G. Celii ,  Scott R. Summerfelt ,  Mahesh Thakre

    发明人： Francis G. Celii ,  Scott R. Summerfelt ,  Mahesh Thakre

    IPC分类号： H01L21/00 ,  H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L21/31122 ,  H01L21/31691 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

    摘要翻译： 本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。 该方法包括用提供相对于硬掩模的实质选择性的高温BCl 3 N 3蚀刻来蚀刻PZT铁电层。 或者，PZT铁电层是使用诸如CHF 3 N 3的低温氟成分蚀刻化学品进行蚀刻，以提供非垂直PZT侧壁轮廓。 这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。

    Method for etching a substrate and a device formed using the method
    8.
    发明授权
    Method for etching a substrate and a device formed using the method 有权
    用于蚀刻基板的方法和使用该方法形成的器件

    公开(公告)号：US07425512B2

    公开(公告)日：2008-09-16

    申请号：US10721932

    申请日：2003-11-25

    申请人： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, Jr. ,  Francis G. Celii

    发明人： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Scott R. Summerfelt ,  Martin G. Albrecht ,  William W. Dostalik, Jr. ,  Francis G. Celii

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31116 ,  H01L21/31616 ,  H01L21/76895 ,  H01L28/55

    摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

    摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。

    Method for forming ferroelectric memory capacitor
    9.
    发明授权
    Method for forming ferroelectric memory capacitor 有权
    形成铁电存储电容器的方法

    公开(公告)号：US07250349B2

    公开(公告)日：2007-07-31

    申请号：US10610498

    申请日：2003-06-30

    申请人： Francis G. Celii ,  Mahesh J. Thakre ,  Scott R. Summerfelt

    发明人： Francis G. Celii ,  Mahesh J. Thakre ,  Scott R. Summerfelt

    IPC分类号： H01L21/22 ,  H01L21/461 ,  H01L21/302

    CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/32136 ,  H01L28/75

    摘要： A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

    摘要翻译： 在电介质层（70）上形成阻挡层，第一金属层，铁电体层，第二金属层和硬掩模层，形成铁电存储电容器。 使用图案化的硬掩模层（255），蚀刻这些层以形成蚀刻的阻挡层（205），蚀刻第一金属层（215）和蚀刻铁电层（225），并蚀刻第二金属层 ）。 蚀刻层形成具有与电介质层（70）的上表面的平面形成角度为78°至88°的侧壁的铁电存储电容器（270）。 用于蚀刻层的工艺是在200℃和500℃之间的温度下进行的等离子体处理。